Fix table optimization when applied on real data type (#5172) (#5173)

docs/CONTRIBUTORS

@@ -19,6 +19,7 @@ Andrew Miloradovsky
 Andrew Nolte
 Anthony Donlon
 Arkadiusz Kozdra
+Arthur Rosa
 Aylon Chaim Porat
 Bartłomiej Chmiel
 Cameron Kirk

src/V3Table.cpp

@@ -89,16 +89,17 @@ public:
         // Create data type
         const int width = elemDType->width();
         AstNodeDType* const subDTypep
-            = elemDType->isString()
+            = elemDType->isString() || elemDType->isDouble()
                   ? elemDType
                   : v3Global.rootp()->findBitDType(width, width, VSigning::UNSIGNED);
         AstUnpackArrayDType* const tableDTypep = new AstUnpackArrayDType{
             m_fl, subDTypep, new AstRange{m_fl, static_cast<int>(size), 0}};
         v3Global.rootp()->typeTablep()->addTypesp(tableDTypep);
         // Create table initializer (with default value 0)
-        AstConst* const defaultp = elemDType->isString()
+        AstConst* const defaultp
-                                       ? new AstConst{m_fl, AstConst::String{}, ""}
+            = elemDType->isString()   ? new AstConst{m_fl, AstConst::String{}, ""}
-                                       : new AstConst{m_fl, AstConst::WidthedValue{}, width, 0};
+              : elemDType->isDouble() ? new AstConst{m_fl, AstConst::RealDouble{}, 0.0}
+                                      : new AstConst{m_fl, AstConst::WidthedValue{}, width, 0};
         m_initp = new AstInitArray{m_fl, tableDTypep, defaultp};
     }
 

test_regress/t/t_opt_table_real.out

@@ -0,0 +1,9 @@
+cyle 0 = 1.0
+cyle 1 = 2.0
+cyle 2 = 3.0
+cyle 3 = 0.0
+cyle 4 = 5.0
+cyle 5 = 6.0
+cyle 6 = 0.0
+cyle 7 = 0.0
+*-* All Finished *-*

test_regress/t/t_opt_table_real.pl

@@ -0,0 +1,28 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2024 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--stats"],
+    );
+
+if ($Self->{vlt_all}) {
+    file_grep($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 1);
+    file_grep($Self->{stats}, qr/ConstPool, Tables emitted\s+(\d+)/i, 1);
+}
+
+execute(
+    check_finished => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;

test_regress/t/t_opt_table_real.v

@@ -0,0 +1,39 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2024.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (
+    // Inputs
+    clk
+);
+  input clk;
+
+  reg [2:0] cyc;
+  real x;
+
+  initial cyc = 0;
+  always @(posedge clk) cyc <= cyc + 1;
+
+  always @(cyc) begin
+    case (cyc)
+      3'd0: x = 1.0;
+      3'd1: x = 2.0;
+      3'd2: x = 3.0;
+      3'd4: x = 5.0;
+      3'd5: x = 6.0;
+      default: x = 0.0;
+    endcase
+  end
+
+  always @(posedge clk) begin
+    $display("cyle %d = %.1f", cyc, x);
+    if (cyc == 7) begin
+      $write("*-* All Finished *-*\n");
+      $finish;
+    end
+  end
+
+endmodule
+;