diff --git a/test_regress/t/t_interface_gen.v b/test_regress/t/t_interface_gen.v index 6c7b88b66..e4dbedad5 100644 --- a/test_regress/t/t_interface_gen.v +++ b/test_regress/t/t_interface_gen.v @@ -6,13 +6,6 @@ // Very simple test for interface pathclearing -`ifdef VCS - `define UNSUPPORTED_MOD_IN_GENS -`endif -`ifdef VERILATOR - `define UNSUPPORTED_MOD_IN_GENS -`endif - module t (/*AUTOARG*/ // Inputs clk @@ -51,38 +44,22 @@ module sub input integer i_value ); -`ifdef UNSUPPORTED_MOD_IN_GENS always @* isub.value = i_value; -`else - generate if (MODE == 1) begin - always @* isub.valuea = i_value; - end - else if (MODE == 2) begin - always @* isub.valueb = i_value; - end - endgenerate -`endif endmodule interface ifc; parameter MODE = 0; // Modports under generates not supported by all commercial simulators -`ifdef UNSUPPORTED_MOD_IN_GENS + integer value; modport out_modport (output value); function integer get_value(); return value; endfunction -`else - generate if (MODE == 0) begin - integer valuea; - modport out_modport (output valuea); - function integer get_valuea(); return valuea; endfunction - end - else begin - integer valueb; - modport out_modport (output valueb); - function integer get_valueb(); return valueb; endfunction - end - endgenerate -`endif + + // IEEE 1800-2017 deprecated alowing modports inside generates + // generate if (MODE == 0) begin + // integer valuea; + // modport out_modport (output valuea); + // function integer get_valuea(); return valuea; endfunction + // end endinterface diff --git a/test_regress/t/t_mod_uselib.py b/test_regress/t/t_mod_uselib.py index c3bd7274f..0b27c3dc0 100755 --- a/test_regress/t/t_mod_uselib.py +++ b/test_regress/t/t_mod_uselib.py @@ -9,7 +9,7 @@ import vltest_bootstrap -test.scenarios('simulator') +test.scenarios('vlt') test.compile() diff --git a/test_regress/t/t_preproc_kwd.py b/test_regress/t/t_preproc_kwd.py index d4f986441..fc5a55e3f 100755 --- a/test_regress/t/t_preproc_kwd.py +++ b/test_regress/t/t_preproc_kwd.py @@ -9,7 +9,7 @@ import vltest_bootstrap -test.scenarios('simulator') +test.scenarios('vlt') test.compile() diff --git a/test_regress/t/t_stream.v b/test_regress/t/t_stream.v index b09985eeb..39f147be4 100644 --- a/test_regress/t/t_stream.v +++ b/test_regress/t/t_stream.v @@ -219,88 +219,88 @@ module t (/*AUTOARG*/ cyc <= cyc + 1; if (cyc == 1) begin - din_i <= 32'h_00_00_00_01; - din_q <= 64'h_00_00_00_00_00_00_00_01; - din_w <= 96'h_00_00_00_00_00_00_00_00_00_00_00_01; + din_i <= 32'h00_00_00_01; + din_q <= 64'h00_00_00_00_00_00_00_01; + din_w <= 96'h00_00_00_00_00_00_00_00_00_00_00_01; - din_lhs <= 4'b_00_01; + din_lhs <= 4'b00_01; end if (cyc == 2) begin - din_i <= 32'h_04_03_02_01; - din_q <= 64'h_08_07_06_05_04_03_02_01; - din_w <= 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01; + din_i <= 32'h04_03_02_01; + din_q <= 64'h08_07_06_05_04_03_02_01; + din_w <= 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01; - din_lhs <= 4'b_01_11; + din_lhs <= 4'b01_11; - if (dout_rhs_ls_i != 32'h_80_00_00_00) $stop; - if (dout_rhs_ls_q != 64'h_80_00_00_00_00_00_00_00) $stop; - if (dout_rhs_ls_w != 96'h_80_00_00_00_00_00_00_00_00_00_00_00) $stop; + if (dout_rhs_ls_i != 32'h80_00_00_00) $stop; + if (dout_rhs_ls_q != 64'h80_00_00_00_00_00_00_00) $stop; + if (dout_rhs_ls_w != 96'h80_00_00_00_00_00_00_00_00_00_00_00) $stop; - if (dout_rhs_rs_i != 32'h_00_00_00_01) $stop; - if (dout_rhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop; - if (dout_rhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop; + if (dout_rhs_rs_i != 32'h00_00_00_01) $stop; + if (dout_rhs_rs_q != 64'h00_00_00_00_00_00_00_01) $stop; + if (dout_rhs_rs_w != 96'h00_00_00_00_00_00_00_00_00_00_00_01) $stop; - if (dout_lhs_ls_a != 2'b_01) $stop; - if (dout_lhs_ls_b != 2'b_00) $stop; + if (dout_lhs_ls_a != 2'b01) $stop; + if (dout_lhs_ls_b != 2'b00) $stop; - if (dout_lhs_rs_a != 2'b_00) $stop; - if (dout_lhs_rs_b != 2'b_01) $stop; + if (dout_lhs_rs_a != 2'b00) $stop; + if (dout_lhs_rs_b != 2'b01) $stop; - if (dout_bhs_rs_i != 32'h_00_00_00_01) $stop; - if (dout_bhs_rs_q != 64'h_00_00_00_00_00_00_00_01) $stop; - if (dout_bhs_rs_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_01) $stop; + if (dout_bhs_rs_i != 32'h00_00_00_01) $stop; + if (dout_bhs_rs_q != 64'h00_00_00_00_00_00_00_01) $stop; + if (dout_bhs_rs_w != 96'h00_00_00_00_00_00_00_00_00_00_00_01) $stop; - if (dout_bhs_ls_i != 32'h_00_00_00_10) $stop; - if (dout_bhs_ls_q != 64'h_00_00_00_00_00_00_01_00) $stop; - if (dout_bhs_ls_w != 96'h_00_00_00_00_00_00_00_00_00_00_00_04) $stop; + if (dout_bhs_ls_i != 32'h00_00_00_10) $stop; + if (dout_bhs_ls_q != 64'h00_00_00_00_00_00_01_00) $stop; + if (dout_bhs_ls_w != 96'h00_00_00_00_00_00_00_00_00_00_00_04) $stop; - if (dout_rhs_ls_i_23_3 != 23'h_10_00_00) $stop; - if (dout_rhs_ls_i_23_4 != 23'h_08_00_00) $stop; + if (dout_rhs_ls_i_23_3 != 23'h10_00_00) $stop; + if (dout_rhs_ls_i_23_4 != 23'h08_00_00) $stop; - if (dout_rhs_ls_q_37_3 != 37'h_04_00_00_00_00) $stop; - if (dout_rhs_ls_q_37_4 != 37'h_02_00_00_00_00) $stop; + if (dout_rhs_ls_q_37_3 != 37'h04_00_00_00_00) $stop; + if (dout_rhs_ls_q_37_4 != 37'h02_00_00_00_00) $stop; end if (cyc == 3) begin // The values below test the strange shift-merge done at the end of // the fast stream operators. // All-1s in the bits being streamed should end up as all-1s. - din_i <= 32'h_00_7f_ff_ff; - din_q <= 64'h_00_00_00_1f_ff_ff_ff_ff; + din_i <= 32'h00_7f_ff_ff; + din_q <= 64'h00_00_00_1f_ff_ff_ff_ff; - if (dout_rhs_ls_i != 32'h_80_40_c0_20) $stop; - if (dout_rhs_ls_q != 64'h_80_40_c0_20_a0_60_e0_10) $stop; - if (dout_rhs_ls_w != 96'h_80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop; + if (dout_rhs_ls_i != 32'h80_40_c0_20) $stop; + if (dout_rhs_ls_q != 64'h80_40_c0_20_a0_60_e0_10) $stop; + if (dout_rhs_ls_w != 96'h80_40_c0_20_a0_60_e0_10_90_50_d0_30) $stop; - if (dout_rhs_rs_i != 32'h_04_03_02_01) $stop; - if (dout_rhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop; - if (dout_rhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; + if (dout_rhs_rs_i != 32'h04_03_02_01) $stop; + if (dout_rhs_rs_q != 64'h08_07_06_05_04_03_02_01) $stop; + if (dout_rhs_rs_w != 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; - if (dout_bhs_ls_i != 32'h_40_30_00_18) $stop; - if (dout_bhs_ls_q != 64'h_06_00_c1_81_41_00_c1_80) $stop; - if (dout_bhs_ls_w != 96'h_30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop; + if (dout_bhs_ls_i != 32'h40_30_00_18) $stop; + if (dout_bhs_ls_q != 64'h06_00_c1_81_41_00_c1_80) $stop; + if (dout_bhs_ls_w != 96'h30_2c_28_20_01_1c_1a_04_14_0c_00_06) $stop; - if (dout_bhs_rs_i != 32'h_04_03_02_01) $stop; - if (dout_bhs_rs_q != 64'h_08_07_06_05_04_03_02_01) $stop; - if (dout_bhs_rs_w != 96'h_0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; + if (dout_bhs_rs_i != 32'h04_03_02_01) $stop; + if (dout_bhs_rs_q != 64'h08_07_06_05_04_03_02_01) $stop; + if (dout_bhs_rs_w != 96'h0c_0b_0a_09_08_07_06_05_04_03_02_01) $stop; - if (dout_lhs_ls_a != 2'b_11) $stop; - if (dout_lhs_ls_b != 2'b_01) $stop; + if (dout_lhs_ls_a != 2'b11) $stop; + if (dout_lhs_ls_b != 2'b01) $stop; - if (dout_lhs_rs_a != 2'b_01) $stop; - if (dout_lhs_rs_b != 2'b_11) $stop; + if (dout_lhs_rs_a != 2'b01) $stop; + if (dout_lhs_rs_b != 2'b11) $stop; - if (dout_rhs_ls_i_23_3 != 23'h_10_08_c0) $stop; - if (dout_rhs_ls_i_23_4 != 23'h_08_10_18) $stop; + if (dout_rhs_ls_i_23_3 != 23'h10_08_c0) $stop; + if (dout_rhs_ls_i_23_4 != 23'h08_10_18) $stop; - if (dout_rhs_ls_q_37_3 != 37'h_04_02_30_10_44) $stop; - if (dout_rhs_ls_q_37_4 != 37'h_02_04_06_08_0a) $stop; + if (dout_rhs_ls_q_37_3 != 37'h04_02_30_10_44) $stop; + if (dout_rhs_ls_q_37_4 != 37'h02_04_06_08_0a) $stop; end if (cyc == 4) begin - if (dout_rhs_ls_i_23_3 != 23'h_7f_ff_ff) $stop; - if (dout_rhs_ls_i_23_4 != 23'h_7f_ff_ff) $stop; + if (dout_rhs_ls_i_23_3 != 23'h7f_ff_ff) $stop; + if (dout_rhs_ls_i_23_4 != 23'h7f_ff_ff) $stop; - if (dout_rhs_ls_q_37_3 != 37'h_1f_ff_ff_ff_ff) $stop; - if (dout_rhs_ls_q_37_4 != 37'h_1f_ff_ff_ff_ff) $stop; + if (dout_rhs_ls_q_37_3 != 37'h1f_ff_ff_ff_ff) $stop; + if (dout_rhs_ls_q_37_4 != 37'h1f_ff_ff_ff_ff) $stop; end if (cyc == 9) begin $write("*-* All Finished *-*\n"); diff --git a/test_regress/t/t_struct_init.v b/test_regress/t/t_struct_init.v index 4f154d190..79f2dd373 100644 --- a/test_regress/t/t_struct_init.v +++ b/test_regress/t/t_struct_init.v @@ -83,31 +83,31 @@ module t; // // Initialization begin - b4_t q = '{1'b1, 1'b1, 1'b0, 1'b0}; + b4_t q; q = '{1'b1, 1'b1, 1'b0, 1'b0}; if (q != 4'b1100) $stop; end begin - b4_t q = '{3{1'b1}, 1'b0}; + b4_t q; q = '{3{1'b1}, 1'b0}; if (q != 4'b1110) $stop; end begin - b4_t q = '{4{1'b1}}; // Repeats the {} + b4_t q; q = '{4{1'b1}}; // Repeats the {} if (q != 4'b1111) $stop; end begin - b4x2_t m = '{4'b1001, '{1'b1, 1'b0, 1'b1, 1'b1}}; + b4x2_t m; m = '{4'b1001, '{1'b1, 1'b0, 1'b1, 1'b1}}; if (m != 8'b10011011) $stop; end begin - b4_t q = '{default:1'b1}; + b4_t q; q = '{default:1'b1}; if (q != 4'b1111) $stop; end begin - b4_t q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0}; + b4_t q; q = '{b0:1'b1, b2:1'b1, b3:1'b1, b1:1'b0}; if (q != 4'b1101) $stop; end begin - b4_t q = '{b2:1'b0, default:1'b1}; + b4_t q; q = '{b2:1'b0, default:1'b1}; if (q != 4'b1011) $stop; end diff --git a/test_regress/t/t_timescale_parse.py b/test_regress/t/t_timescale_parse.py index f37ad07c8..9d1dcec8d 100755 --- a/test_regress/t/t_timescale_parse.py +++ b/test_regress/t/t_timescale_parse.py @@ -9,7 +9,7 @@ import vltest_bootstrap -test.scenarios('simulator') +test.scenarios('vlt') test.compile(make_top_shell=False, make_main=False, verilator_flags2=["--exe", test.pli_filename]) diff --git a/test_regress/t/t_trace_primitive.v b/test_regress/t/t_trace_primitive.v index 176c053ca..fe08ff8ca 100644 --- a/test_regress/t/t_trace_primitive.v +++ b/test_regress/t/t_trace_primitive.v @@ -30,9 +30,17 @@ module t endmodule primitive CINV (a, b); -output b; -input a; -assign b = ~a; + output b; + input a; +`ifdef VERILATOR + assign b = ~a; +`else + table + //b a + 0 : ? : 1; + 1 : ? : 0; + endtable +`endif endprimitive