github/verilator
1
0
Fork 1
mirror of https://github.com/verilator/verilator.git synced 2025-04-16 01:26:54 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fix comparing ranged slices of unpacked arrays.

Browse Source
This commit is contained in:
Wilson Snyder 2022-11-11 18:01:30 -05:00
parent b2e61425d6
commit 227e61f891
4 changed files with 53 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
Changes
View File

@ -20,6 +20,7 @@ Verilator 5.003 devel
* Fix missing UNUSED warnings with --coverage (#3736). [alejandro-castro-ortegon]
* Fix tracing parameters overridden with -G (#3723). [Iztok Jeras]
* Fix wait 0.
* Fix comparing ranged slices of unpacked arrays.
Verilator 5.002 2022-10-29

10
src/V3Slice.cpp
View File

@ -185,14 +185,12 @@ class SliceVisitor final : public VNVisitor {
<< nodep->rhsp()->prettyTypeName()
<< " on non-slicable (e.g. non-vector) right-hand-side operand");
} else {
for (int index = 0; index < adtypep->rangep()->elementsConst(); ++index) {
const int elements = adtypep->rangep()->elementsConst();
for (int offset = 0; offset < elements; ++offset) {
// EQ(a,b) -> LOGAND(EQ(ARRAYSEL(a,0), ARRAYSEL(b,0)), ...[1])
AstNodeBiop* const clonep
= VN_AS(nodep->cloneType(
new AstArraySel{nodep->fileline(),
nodep->lhsp()->cloneTree(false), index},
new AstArraySel{nodep->fileline(),
nodep->rhsp()->cloneTree(false), index}),
= VN_AS(nodep->cloneType(cloneAndSel(nodep->lhsp(), elements, offset),
cloneAndSel(nodep->rhsp(), elements, offset)),
NodeBiop);
if (!logp) {
logp = clonep;

21
test_regress/t/t_slice_cmp.pl Executable file
View File

@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2021 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

27
test_regress/t/t_slice_cmp.v Normal file
View File

@ -0,0 +1,27 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2022 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/);
bit a [5:0];
bit b [5:0];
initial begin
a = '{1, 1, 1, 0, 0, 0};
b = '{0, 0, 0, 1, 1, 1};
$display(":assert: ('%b%b%b_%b%b%b' == '111_000')",
a[5], a[4], a[3], a[2], a[1], a[0]);
$display(":assert: ('%b%b%b_%b%b%b' == '000_111')",
b[5], b[4], b[3], b[2], b[1], b[0]);
if ((a[5:3] == b[2:0]) != 1'b1) $stop;
if ((a[5:3] != b[2:0]) != 1'b0) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule