From 221fecad0be977a1bbf22b1568495b23fdc958bf Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Tue, 11 Jun 2024 19:47:53 -0400 Subject: [PATCH] Commentary --- README.rst | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/README.rst b/README.rst index 754523f6b..1a8f34017 100644 --- a/README.rst +++ b/README.rst @@ -87,12 +87,11 @@ thread is about 100 times faster than interpreted Verilog simulators such as `Icarus Verilog`_. Another 2-10x speedup might be gained from multithreading (yielding 200-1000x total over interpreted simulators). -Verilator has typically similar or better performance versus -closed-source Verilog simulators (e.g., Carbon Design Systems Carbonator, -Modelsim/Questa, Cadence Incisive/NC-Verilog, Synopsys VCS, VTOC, and -Pragmatic CVer/CVC). But, Verilator is open-sourced, so you can spend on -computes rather than licenses. Thus, Verilator gives you the best -simulation cycles/dollar. +Verilator has typically similar or better performance versus closed-source +Verilog simulators (e.g., Aldec Riviera-Pro, Cadence Incisive/NC-Verilog, +Mentor ModelSim/Questa, Synopsys VCS, VTOC, and Pragmatic CVer/CVC). But, +Verilator is open-sourced, so you can spend on computes rather than +licenses. Thus, Verilator gives you the best simulation cycles/dollar. Installation & Documentation