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Allow dotted references of arrayed cells

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git-svn-id: file://localhost/svn/verilator/trunk/verilator@777 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2006-09-06 17:48:41 +00:00
parent 0a765fbb54
commit 21eb939f37
5 changed files with 58 additions and 31 deletions
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7
bin/verilator
View File

@ -1115,8 +1115,11 @@ always @* to prevent these issues.)
=head2 Dotted cross-hierarchy references
Verilator supports dotted references to variables, functions and tasks in
different modules. However, references into named blocks, function-local
variables, and arrayed instances are not supported.
different modules. However, references into named blocks and function-local
variables are not supported. References into generate statements and
arrayed instances are possible, but may use different names from the
Verilog standard; arrayed instances are named {cellName}__{instanceNumber},
while for generates, it's genblk{instanceNumber} or genfor{loopCount}.
=head2 Latches

56
src/V3LinkDot.cpp
View File

@ -68,12 +68,18 @@ public:
void insertSubcellName(const string& name, LinkDotBaseVertex* toVertexp) {
m_nameToVtxMap.insert(make_pair(name,toVertexp));
}
LinkDotBaseVertex* findSubcell(const string& name) {
LinkDotBaseVertex* findSubcell(const string& name, const string& altname) {
// Find a vertex under this one by name.
// We could walk the edge top() list, but that would be O(n) for large lists of cells
NameVtxMap::iterator iter = m_nameToVtxMap.find(name);
if (iter == m_nameToVtxMap.end()) return NULL;
else return iter->second;
{
NameVtxMap::iterator iter = m_nameToVtxMap.find(name);
if (iter != m_nameToVtxMap.end()) return iter->second;
}
if (altname != "") {
NameVtxMap::iterator iter = m_nameToVtxMap.find(altname);
if (iter != m_nameToVtxMap.end()) return iter->second;
}
return NULL;
}
};
@ -134,18 +140,20 @@ private:
// MEMBERS
LinkDotGraph m_graph; // Graph of hiearchy
NameScopeMap m_nameScopeMap; // Hash of scope referenced by textual name
bool m_forPrearray; // Compress cell__[array] refs
bool m_forScopeCreation; // Remove VarXRefs for V3Scope
public:
static int debug() { return V3Error::debugDefault(); }
// static int debug() { return 9; }
// CONSTRUCTORS
LinkDotState(bool forScopeCreation) {
LinkDotState(bool forPrearray, bool forScopeCreation) {
UINFO(4,__FUNCTION__<<": "<<endl);
m_forPrearray = forPrearray;
m_forScopeCreation = forScopeCreation;
//VV***** We reset all userp() on each netlist!!!
AstNode::userClearTree();
AstNode::user2ClearTree();
m_forScopeCreation = forScopeCreation;
}
~LinkDotState() {}
@ -234,18 +242,26 @@ public:
leftname = "";
}
baddot = ident; // So user can see where they botched it
string altIdent = "";
if (m_forPrearray) {
// Cell foo__[array] before we've expanded arrays is just foo.
if ((pos = ident.find("__")) != string::npos) {
altIdent = ident.substr(0,pos);
}
}
UINFO(8," id "<<ident<<" left "<<leftname<<" at "<<cellVxp<<endl);
// Spec says; Look at exiting module (cellnames then modname),
// then look up (inst name or modname)
if (firstId) {
// Check this module - subcellnames
if (LinkDotBaseVertex* findVxp = cellVxp->findSubcell(ident)) {
if (LinkDotBaseVertex* findVxp = cellVxp->findSubcell(ident, altIdent)) {
cellVxp = findVxp;
}
// Check this module - cur modname
else if (cellVxp->modName() == ident) {}
// Check this module - cur cellname
else if (cellVxp->cellName() == ident) {}
else if (cellVxp->cellName() == altIdent) {}
// Move up and check cellname + modname
else {
while (cellVxp) {
@ -253,10 +269,11 @@ public:
if (cellVxp) {
UINFO(9,"\t\tUp to "<<cellVxp<<endl);
if (cellVxp->modName() == ident
|| cellVxp->cellName() == ident) {
|| cellVxp->cellName() == ident
|| cellVxp->cellName() == altIdent) {
break;
}
else if (LinkDotBaseVertex* findVxp = cellVxp->findSubcell(ident)) {
else if (LinkDotBaseVertex* findVxp = cellVxp->findSubcell(ident, altIdent)) {
cellVxp = findVxp;
break;
}
@ -265,7 +282,7 @@ public:
if (!cellVxp) return NULL; // Not found
}
} else { // Searching for middle submodule, must be a cell name
if (LinkDotBaseVertex* findVxp = cellVxp->findSubcell(ident)) {
if (LinkDotBaseVertex* findVxp = cellVxp->findSubcell(ident, altIdent)) {
cellVxp = findVxp;
} else {
return NULL; // Not found
@ -606,22 +623,15 @@ public:
//######################################################################
// Link class functions
void V3LinkDot::linkDot(AstNetlist* rootp) {
void V3LinkDot::linkDotGuts(AstNetlist* rootp, bool prearray, bool scoped) {
UINFO(2,__FUNCTION__<<": "<<endl);
if (LinkDotState::debug()>=5) v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("prelinkdot.tree"));
LinkDotState state (false);
LinkDotState state (prearray,scoped);
LinkDotFindVisitor visitor(rootp,&state);
state.dump();
LinkDotResolveVisitor visitorb(rootp,&state);
}
void V3LinkDot::linkDotScope(AstNetlist* rootp) {
UINFO(2,__FUNCTION__<<": "<<endl);
if (LinkDotState::debug()>=5) v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("prelinkdot.tree"));
LinkDotState state (true);
LinkDotFindVisitor visitor(rootp,&state);
// Process AstScope's. This needs to be separate pass after whole hiearchy graph created.
LinkDotScopeVisitor visitors(rootp,&state);
if (scoped) {
// Process AstScope's. This needs to be separate pass after whole hierarchy graph created.
LinkDotScopeVisitor visitors(rootp,&state);
}
state.dump();
LinkDotResolveVisitor visitorb(rootp,&state);
}

7
src/V3LinkDot.h
View File

@ -28,9 +28,12 @@
//============================================================================
class V3LinkDot {
private:
static void linkDotGuts(AstNetlist* nodep, bool preparam, bool scoped);
public:
static void linkDot(AstNetlist* nodep);
static void linkDotScope(AstNetlist* nodep);
static void linkDotPrearrayed(AstNetlist* nodep) { linkDotGuts(nodep,true,false); }
static void linkDotArrayed(AstNetlist* nodep) { linkDotGuts(nodep,false,false); }
static void linkDotScope(AstNetlist* nodep) { linkDotGuts(nodep,false,true); }
};
#endif // Guard

8
src/Verilator.cpp
View File

@ -109,7 +109,7 @@ void process () {
// Cross-link signal names
V3Link::link(v3Global.rootp());
// Cross-link dotted hierarchical references
V3LinkDot::linkDot(v3Global.rootp());
V3LinkDot::linkDotPrearrayed(v3Global.rootp());
// Correct state we couldn't know at parse time, repair SEL's, set lvalue's
V3LinkResolve::linkResolve(v3Global.rootp());
v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("link.tree"));
@ -120,7 +120,7 @@ void process () {
// Remove parameters by cloning modules to de-parameterized versions
// This requires some width calculations and constant propagation
V3Param::param(v3Global.rootp());
V3LinkDot::linkDot(v3Global.rootp()); // Cleanup as made new modules
V3LinkDot::linkDotPrearrayed(v3Global.rootp()); // Cleanup as made new modules
v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("param.tree"));
V3Error::abortIfErrors();
@ -169,7 +169,7 @@ void process () {
V3Const::constifyAllLint(v3Global.rootp());
v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("const.tree"));
// Remove cell arrays (must be between V3Width and tasking)
// Remove cell arrays (must be between V3Width and scoping)
V3Inst::dearrayAll(v3Global.rootp());
//v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("dearray.tree"));
@ -189,7 +189,7 @@ void process () {
if (v3Global.opt.oInline()) {
V3Inline::inlineAll(v3Global.rootp());
v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("inline.tree"));
V3LinkDot::linkDot(v3Global.rootp()); // Cleanup as made new modules
V3LinkDot::linkDotArrayed(v3Global.rootp()); // Cleanup as made new modules
//v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("linkdot.tree"));
}

11
test_regress/t/t_inst_array.v
View File

@ -11,6 +11,7 @@ module t (/*AUTOARG*/
input clk;
integer cyc; initial cyc=1;
parameter ONE = 1;
wire [17:10] bitout;
reg [7:0] allbits;
@ -18,6 +19,8 @@ module t (/*AUTOARG*/
sub sub [7:0] (allbits, onebit, bitout);
integer x;
always @ (posedge clk) begin
//$write("%x\n", bitout);
if (cyc!=0) begin
@ -33,6 +36,14 @@ module t (/*AUTOARG*/
end
if (cyc==3) begin
if (bitout !== 8'h41) $stop;
`ifdef verilator // Hacky array subscripting
if (sub__0.bitout !== 1'b1) $stop;
if (sub__1.bitout !== 1'b0) $stop;
`else
if (sub[0].bitout !== 1'b1) $stop;
if (sub[1].bitout !== 1'b0) $stop;
if (sub[ONE].bitout !== 1'b0) $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end