diff --git a/Changes b/Changes index 612ba975d..58a437c5f 100644 --- a/Changes +++ b/Changes @@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks! *** Optimize two-level shift and and/or trees, +23% on one test. +**** Fix arrayed variables under function not compiling, bug44. [Ralf Karge] + **** Fix --output-split-cfuncs to also split trace code. [Niranjan Prabhu] **** Fix 'bad select range' warning missing some cases, bug43. [Lane Brooks] diff --git a/bin/verilator_difftree b/bin/verilator_difftree index 6240dc52b..49ae3c3cc 100755 --- a/bin/verilator_difftree +++ b/bin/verilator_difftree @@ -1,18 +1,7 @@ : # -*-Mode: perl;-*- use perl, wherever it is eval 'exec perl -wS $0 ${1+"$@"}' if 0; -###################################################################### -# -# Copyright 2005-2008 by Wilson Snyder . This -# program is free software; you can redistribute it and/or modify it under -# the terms of either the GNU Lesser General Public License or the Perl -# Artistic License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# +# See copyright, etc in below POD section. ###################################################################### require 5.006_001; @@ -32,14 +21,16 @@ use vars qw ($Debug); $Debug = 0; my $Opt_A; my $Opt_B; +my $Opt_Lineno = 1; autoflush STDOUT 1; autoflush STDERR 1; Getopt::Long::config ("no_auto_abbrev"); if (! GetOptions ( - "help" => \&usage, - "debug" => \&debug, - "<>" => \¶meter, - )) { + "help" => \&usage, + "debug" => \&debug, + "<>" => \¶meter, + "lineno!" => \$Opt_Lineno, + )) { die "%Error: Bad usage, try 'verilator_difftree --help'\n"; } @@ -105,6 +96,7 @@ sub filter { next if $line =~ / This=/; $line =~ s/0x[a-f0-9]+/0x/g; $line =~ s///g; + $line =~ s/{\d+}/{}/g if !$Opt_Lineno; print $f2 $line; } $f1->close; @@ -172,6 +164,10 @@ directories, ignoring irrelevant pointer differences. Displays this message and program version and exits. +=item --nolineno + +Do not show differences in line numbering. + =back =head1 DISTRIBUTION diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index 02dd7924b..d5f58b5f6 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -284,8 +284,12 @@ public: init(); combineType(type); if (examplep->rangep()) { + // Creating is faster than cloning; know have constant args setOp1p(new AstRange(fl, examplep->msb(), examplep->lsb())); } + if (examplep->arraysp()) { + setOp2p(examplep->arraysp()->cloneTree(true)); + } width(msb()-lsb()+1,0); } virtual ~AstVar() {} diff --git a/test_regress/t/t_mem_func.pl b/test_regress/t/t_mem_func.pl new file mode 100755 index 000000000..cdae47250 --- /dev/null +++ b/test_regress/t/t_mem_func.pl @@ -0,0 +1,17 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# General Public License or the Perl Artistic License. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_mem_func.v b/test_regress/t/t_mem_func.v new file mode 100644 index 000000000..106b36b27 --- /dev/null +++ b/test_regress/t/t_mem_func.v @@ -0,0 +1,123 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2008 by Wilson Snyder. + +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + + integer cyc=0; + reg [63:0] crc; + reg [63:0] sum; + + /*AUTOWIRE*/ + // Beginning of automatic wires (for undeclared instantiated-module outputs) + wire [2:0] q; // From test of Test.v + // End of automatics + + Test test ( + // Outputs + .q (q[2:0]), + // Inputs + .clk (clk), + .reset_l (crc[0]), + .enable (crc[2]), + .q_var0 (crc[19:10]), + .q_var2 (crc[29:20]), + .q_var4 (crc[39:30]), + .q_var6 (crc[49:40]) + /*AUTOINST*/); + + // Aggregate outputs into a single result vector + wire [63:0] result = {61'h0,q}; + + // Test loop + always @ (posedge clk) begin +`ifdef TEST_VERBOSE + $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result); +`endif + cyc <= cyc + 1; + crc <= {crc[62:0], crc[63]^crc[2]^crc[0]}; + sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]}; + if (cyc==0) begin + // Setup + crc <= 64'h5aef0c8d_d70a4497; + end + else if (cyc<10) begin + sum <= 64'h0; + end + else if (cyc<90) begin + end + else if (cyc==99) begin + $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum); + if (crc !== 64'hc77bb9b3784ea091) $stop; +`define EXPECTED_SUM 64'h58b162c58d6e35ba + if (sum !== `EXPECTED_SUM) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end +endmodule + + +module Test + ( + input clk, + input reset_l, + input enable, + + input [ 9:0] q_var0, + input [ 9:0] q_var2, + input [ 9:0] q_var4, + input [ 9:0] q_var6, + + output reg [2:0] q + ); + + reg [7:0] p1_r [6:0]; + + always @(posedge clk) begin + if (!reset_l) begin + p1_r[0] <= 'b0; + p1_r[1] <= 'b0; + p1_r[2] <= 'b0; + p1_r[3] <= 'b0; + p1_r[4] <= 'b0; + p1_r[5] <= 'b0; + p1_r[6] <= 'b0; + end + else if (enable) begin : pass1 + match(q_var0, q_var2, q_var4, q_var6); + end + end + + // verilator lint_off WIDTH + always @(posedge clk) begin : l + reg [10:0] bd; + reg [3:0] idx; + + q = 0; + bd = 0; + for (idx=0; idx<7; idx=idx+1) begin + q = idx+1; + bd = bd + p1_r[idx]; + end + end + + + task match; + input [9:0] p0, p1, p2, p3; + reg [9:0] p[3:0]; + begin + p[0] = p0; + p[1] = p1; + p[2] = p2; + p[3] = p3; + p1_r[0] = p[0]; + p1_r[1] = p[1]; + end + endtask +endmodule