diff --git a/Changes b/Changes
index 414ff133e..e077cf002 100644
--- a/Changes
+++ b/Changes
@@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Support '#' comments in $readmem, bug1411. [Frederick Requin]
 
+****  Support "'dx" constants, bug1423. [Udi Finkelstein]
+
 ****  Add error when use parameters without value, bug1424. [Peter Gerst]
 
 ****  Fix missing VL_SHIFTL_ errors, bug1412, bug1415. [Larry Lee]
diff --git a/src/V3Number.cpp b/src/V3Number.cpp
index 5df629cdf..aba95a87a 100644
--- a/src/V3Number.cpp
+++ b/src/V3Number.cpp
@@ -153,18 +153,16 @@ V3Number::V3Number(FileLine* fileline, const char* sourcep) {
 		got_01 = 1;
 		break;
 	    }
-	    case 'z': case '?': {
-		if (!m_sized)  m_fileline->v3error("Unsized X/Z/? not legal in decimal constant: "<<*cp);
-		setAllBitsZ();
-		got_z = 1;
-		break;
-	    }
-	    case 'x': {
-		if (!m_sized)  m_fileline->v3error("Unsized X/Z/? not legal in decimal constant: "<<*cp);
-		got_x = 1;
-		setAllBitsX();
-		break;
-	    }
+            case 'z': case '?': {
+                got_z = 1;
+                setAllBitsZ();
+                break;
+            }
+            case 'x': {
+                got_x = 1;
+                setAllBitsX();
+                break;
+            }
 	    case '_': break;
 	    default: {
 		m_fileline->v3error("Illegal character in decimal constant: "<<*cp);
diff --git a/test_regress/t/t_const.pl b/test_regress/t/t_const.pl
new file mode 100755
index 000000000..b1acebe26
--- /dev/null
+++ b/test_regress/t/t_const.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2004 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_const.v b/test_regress/t/t_const.v
new file mode 100644
index 000000000..ccdc90633
--- /dev/null
+++ b/test_regress/t/t_const.v
@@ -0,0 +1,21 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2019 by Wilson Snyder.
+
+module t (/*AUTOARG*/);
+
+   initial begin
+      // verilator lint_off WIDTH
+      if (32'hxxxxxxxx !== 'hx) $stop;
+      if (32'hzzzzzzzz !== 'hz) $stop;
+      if (32'h???????? !== 'h?) $stop;
+      if (32'hxxxxxxxx !== 'dx) $stop;
+      if (32'hzzzzzzzz !== 'dz) $stop;
+      if (32'h???????? !== 'd?) $stop;
+      // verilator lint_on WIDTH
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule