Fix loss of warning source content with `line enter (due to earlier commit 472ad90d83).

This commit is contained in:
Wilson Snyder 2023-10-10 20:40:21 -04:00
parent 7ce0bd1181
commit 1fd8e772b0
7 changed files with 52 additions and 1 deletions

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@ -210,6 +210,7 @@ public:
lineno(num);
m_contentLineno = static_cast<unsigned>(num);
}
void contentLinenoFrom(const FileLine* fromp) { m_contentLineno = fromp->m_contentLineno; }
void lineno(int num) {
m_firstLineno = num;
m_lastLineno = num;

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@ -85,8 +85,11 @@ void V3ParseImp::lexPpline(const char* textp) {
lexFileline(newFl);
lexFileline()->parent(prevFl);
} else if (enterExit == 2) { // Exit
const FileLine* const prevFl = lexFileline();
if (FileLine* upFl = lexFileline()->parent()) {
lexFileline(upFl); // Restore warning state to upper file
// Must copy upFl as may be existing nodes that use the FileLine value
lexFileline(new FileLine{upFl}); // Restore warning state to upper file
lexFileline()->contentLinenoFrom(prevFl);
}
}
if (enterExit != -1) { // Line/fn change

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@ -1,5 +1,7 @@
%Warning-WIDTHTRUNC: t/t_lint_warn_incfile2_bad.v:13:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
: ... note: In instance 't'
13 | int warn_t = 64'h1;
| ^~~~~
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
%Error: Exiting due to

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@ -0,0 +1,7 @@
%Warning-WIDTHTRUNC: the_line_file:13:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
: ... note: In instance 't'
13 | int warn_t = 64'h1;
| ^~~~~
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
%Error: Exiting due to

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@ -0,0 +1,22 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2008 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
lint(
# See also t/t_lint_warn_incfile1_bad
# See also t/t_vlt_warn_file_bad
verilator_flags2 => ["--no-std"],
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

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@ -0,0 +1,14 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
// Check that `line `__LINE__ still shows proper warning context
`line `__LINE__ "the_line_file" 1
`line `__LINE__ "the_line_file" 2
module t;
int warn_t = 64'h1; // Not suppressed - should warn
endmodule

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@ -1,5 +1,7 @@
%Warning-WIDTHTRUNC: t/t_vlt_warn_file_bad.v:11:17: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS's CONST '64'h1' generates 64 bits.
: ... note: In instance 't'
11 | int warn_t = 64'h1;
| ^~~~~
... For warning description see https://verilator.org/warn/WIDTHTRUNC?v=latest
... Use "/* verilator lint_off WIDTHTRUNC */" and lint_on around source to disable this message.
%Error: Exiting due to