From 1f714c6813e74dfaaaa4d358f047a7c03f532099 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 11 May 2019 18:42:27 -0400 Subject: [PATCH] Commentary: Spelling fixes. --- bin/verilator | 12 ++++++------ bin/verilator_profcfunc | 2 +- internals.pod | 4 ++-- src/V3AstNodes.h | 2 +- src/V3EmitC.cpp | 2 +- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/bin/verilator b/bin/verilator index 38641a47c..f59a41fde 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1533,7 +1533,7 @@ ensure that X E 1 triggers a C. B Some users have reported that using this option can affect convergence, and that it may be necessary to use --converge-limit to increase the number of convergence iterations. This may be another -indication of problems with the modelled design that should be addressed. +indication of problems with the modeled design that should be addressed. =item --xml-only @@ -1604,7 +1604,7 @@ posedge eval() and one negedge eval(). =item +verilator+rand+reset+I -When a model was Verilated using "-x-inital unique", sets the +When a model was Verilated using "-x-initial unique", sets the initialization technique. 0 = Reset to zeros. 1 = Reset to all-ones. 2 = Randomize. See L. @@ -2353,7 +2353,7 @@ provides one of those threads, and the generated model will create and manage the other N-1 threads. It's the client's responsibility not to oversubscribe the available CPU cores. Under CPU oversubscription, the Verilated model should not livelock nor deadlock, however, you can expect -performance to be far worse than it would be with proper stoichiometry of +performance to be far worse than it would be with proper ratio of threads and CPU cores. With --trace-fst-thread, tracing occurs in a separate thread from the main @@ -2404,7 +2404,7 @@ completing after the $stop or $finish. If using --coverage, the coverage routines are fully thread safe. If using --dpi, Verilator assumes pure DPI imports are thread safe, -balancing performance versus saftey. See --threads-dpi. +balancing performance versus safety. See --threads-dpi. If using --savable, the save/restore classes are not multithreaded and are must be called only by the eval thread. @@ -2909,7 +2909,7 @@ clock pins to be sc_clocks and this is no longer needed. Used after a port declaration. It sets the port to be of sc_bv> type, instead of bool, vluint32_t or vluint64_t. This may be useful if -the port width is parametrized and different of such modules interface +the port width is parameterized and different of such modules interface a templated module (such as a transactor) or for other reasons. In general you should avoid using this attribute when not necessary as with increasing usage of sc_bv the performance increases significantly. @@ -3300,7 +3300,7 @@ $value$plusargs. Not supported as Verilator needs to determine all formatting at compile time. Generally you can just ifdef them out for no ill effect. Note also -VL_TIME_MULTIPLER can be defined at compile time to move the decimal point +VL_TIME_MULTIPLIER can be defined at compile time to move the decimal point when displaying all times, model wide. =back diff --git a/bin/verilator_profcfunc b/bin/verilator_profcfunc index 22eb9afbe..b1a2e9cfa 100755 --- a/bin/verilator_profcfunc +++ b/bin/verilator_profcfunc @@ -212,7 +212,7 @@ verilator_profcfunc - Read gprof report created with --prof-cfuncs =head1 DESCRIPTION Verilator_profcfunc reads a profile report created by gprof. The names of -the functions are then transformed, assuming the user used verilator's +the functions are then transformed, assuming the user used Verilator's --prof-cfuncs, and a report printed showing the percentage of time, etc, in each Verilog block. diff --git a/internals.pod b/internals.pod index af3e847b3..81490329d 100644 --- a/internals.pod +++ b/internals.pod @@ -302,7 +302,7 @@ serial mode; that is a possible area for improvement.) =item C -To allow the verilated model to run in parallel with the testbench, it +To allow the Verilated model to run in parallel with the testbench, it might be nice to support "wave" scheduling, in which work on a cycle begins before eval() is called or continues after eval() returns. For now all work on a cycle happens during the eval() call, leaving Verilator's threads @@ -826,7 +826,7 @@ level. For example after inlining: The textual name of this node AST type (always in capitals). Many of these correspond directly to Verilog entities (for example C and -C), but others are internal to Verialtor (for example C and +C), but others are internal to Verilator (for example C and C). =item Address of the node diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h index d7fd9d351..544dbeac6 100644 --- a/src/V3AstNodes.h +++ b/src/V3AstNodes.h @@ -2368,7 +2368,7 @@ public: }; class AstCondBound : public AstNodeCond { - // Conditional ?: statement, specially made for saftey checking of array bounds + // Conditional ?: statement, specially made for safety checking of array bounds // Parents: MATH // Children: MATH public: diff --git a/src/V3EmitC.cpp b/src/V3EmitC.cpp index 64e87fe1b..c7ec3c129 100644 --- a/src/V3EmitC.cpp +++ b/src/V3EmitC.cpp @@ -373,7 +373,7 @@ public: puts("VL_FCLOSE_I("); iterateAndNextNull(nodep->filep()); puts("); "); - iterateAndNextNull(nodep->filep()); // For saftey, so user doesn't later WRITE with it. + iterateAndNextNull(nodep->filep()); // For safety, so user doesn't later WRITE with it. puts("=0;\n"); } virtual void visit(AstFFlush* nodep) {