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commit
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@ -1478,7 +1478,7 @@ class VlClass VL_NOT_FINAL : public VlDeletable {
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public:
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// CONSTRUCTORS
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VlClass() { refCountInc(); }
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VlClass(const VlClass& copied) {}
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VlClass(const VlClass& copied) { refCountInc(); }
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~VlClass() override = default;
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};
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21
test_regress/t/t_class_copy2.pl
Executable file
21
test_regress/t/t_class_copy2.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2020 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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36
test_regress/t/t_class_copy2.v
Normal file
36
test_regress/t/t_class_copy2.v
Normal file
@ -0,0 +1,36 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Antmicro Ltd.
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// SPDX-License-Identifier: CC0-1.0
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`define stop $stop
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`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
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class Cls;
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bit x = 1;
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endclass
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module t (/*AUTOARG*/);
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Cls obj1;
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Cls obj2;
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initial begin
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obj1 = new;
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`checkh(obj1.x, 1);
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obj1.x = 0;
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obj2 = new obj1;
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`checkh(obj2.x, 0);
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obj2.x = 1;
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`checkh(obj1.x, 0);
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`checkh(obj2.x, 1);
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obj2.x = 0;
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`checkh(obj2.x, 0);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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