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Optimize display+display statements.
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@ -1906,7 +1906,7 @@ private:
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}
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else if (0 // Disabled, as vpm assertions are faster without due to short-circuiting
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&& operandIfIf(nodep)) {
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UINFO(0,"IF({a}) IF({b}) => IF({a} && {b})"<<endl);
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UINFO(9,"IF({a}) IF({b}) => IF({a} && {b})"<<endl);
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AstNodeIf* lowerIfp = nodep->ifsp()->castNodeIf();
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AstNode* condp = nodep->condp()->unlinkFrBack();
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AstNode* lowerIfsp = lowerIfp->ifsp()->unlinkFrBackWithNext();
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@ -1922,6 +1922,49 @@ private:
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}
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}
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virtual void visit(AstDisplay* nodep) {
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// DISPLAY(SFORMAT(text1)),DISPLAY(SFORMAT(text2)) -> DISPLAY(SFORMAT(text1+text2))
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nodep->iterateChildren(*this);
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if (stmtDisplayDisplay(nodep)) return;
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}
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bool stmtDisplayDisplay(AstDisplay* nodep) {
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// DISPLAY(SFORMAT(text1)),DISPLAY(SFORMAT(text2)) -> DISPLAY(SFORMAT(text1+text2))
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if (!m_modp) return false; // Don't optimize under single statement
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if (!nodep->backp()) return false;
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AstDisplay* prevp = nodep->backp()->castDisplay();
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if (!prevp) return false;
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if (!((prevp->displayType() == nodep->displayType())
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|| (prevp->displayType() == AstDisplayType::DT_WRITE
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&& nodep->displayType() == AstDisplayType::DT_DISPLAY)
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|| (prevp->displayType() == AstDisplayType::DT_DISPLAY
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&& nodep->displayType() == AstDisplayType::DT_WRITE)))
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return false;
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if ((prevp->filep() && !nodep->filep())
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|| (!prevp->filep() && nodep->filep())
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|| !prevp->filep()->sameTree(nodep->filep())) return false;
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if (!prevp->fmtp() || prevp->fmtp()->nextp()
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|| !nodep->fmtp() || nodep->fmtp()->nextp()) return false;
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AstSFormatF* pformatp = prevp->fmtp();
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if (!pformatp || pformatp->exprsp() || pformatp->scopeNamep()) return false;
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AstSFormatF* nformatp = nodep->fmtp();
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if (!nformatp || nformatp->exprsp() || nformatp->scopeNamep()) return false;
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//
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UINFO(9,"DISPLAY(SF({a})) DISPLAY(SF({b})) -> DISPLAY(SF({a}+{b}))"<<endl);
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// Convert DT_DISPLAY to DT_WRITE as may allow later optimizations
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if (prevp->displayType() == AstDisplayType::DT_DISPLAY) {
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prevp->displayType(AstDisplayType::DT_WRITE);
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pformatp->text(pformatp->text()+"\n");
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}
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// We can't replace prev() as the edit tracking iterators will get confused.
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// So instead we edit the prev note itself.
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if (prevp->addNewline()) pformatp->text(pformatp->text()+"\n");
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pformatp->text(pformatp->text()+nformatp->text());
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if (!prevp->addNewline() && nodep->addNewline()) {
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pformatp->text(pformatp->text()+"\n");
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}
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nodep->unlinkFrBack()->deleteTree(); VL_DANGLING(nodep);
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return true;
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}
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virtual void visit(AstSFormatF* nodep) {
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// Substitute constants into displays. The main point of this is to
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// simplify assertion methodologies which call functions with display's.
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@ -1960,7 +2003,7 @@ private:
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UINFO(9," DispConst: "<<fmt<<" -> "<<out<<" for "<<argp<<endl);
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// fmt = out w/ replace % with %% as it must be literal.
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fmt = VString::quotePercent(out);
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argp->unlinkFrBack()->deleteTree();
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argp->unlinkFrBack()->deleteTree(); VL_DANGLING(argp);
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}
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argp=nextp;
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}
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@ -166,7 +166,7 @@ private:
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}
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}
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// Not really any way the user could do this, and we'd need to come up with some return value
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//newfuncp->addStmtsp(new AstDisplay (newfuncp->fileline(), AstDisplayType::DT_DISPLAY,
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//newfuncp->addStmtsp(new AstDisplay (newfuncp->fileline(), AstDisplayType::DT_WARNING,
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// string("%%Error: ")+name+"() called with bad scope", NULL));
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//newfuncp->addStmtsp(new AstStop (newfuncp->fileline()));
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if (debug()>=9) newfuncp->dumpTree(cout," newfunc: ");
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27
test_regress/t/t_display_merge.pl
Executable file
27
test_regress/t/t_display_merge.pl
Executable file
@ -0,0 +1,27 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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verilator_flags2=>["--stats"],
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);
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execute (
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check_finished=>1,
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expect=> (quotemeta(
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'Merge:
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This should merge
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*-* All Finished *-*')
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.'.*')
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);
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file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}__stats.txt",
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qr/Node count, DISPLAY \s+ 5 \s+ 1 \s+ 1 \s+ 1/);
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ok(1);
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1;
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15
test_regress/t/t_display_merge.v
Normal file
15
test_regress/t/t_display_merge.v
Normal file
@ -0,0 +1,15 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Wilson Snyder.
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module t (/*AUTOARG*/);
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initial begin
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$display("Merge:");
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$write("This ");
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$write("should ");
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$display("merge");
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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