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Fix vpiLeftRange on little-endian memories (#2696).
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@ -27,6 +27,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
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**** Fix genblk naming to match IEEE (#2686). [tinshark]
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**** Fix genblk naming to match IEEE (#2686). [tinshark]
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**** Fix vpiLeftRange on little-endian memories (#2696). [Marlon James]
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**** Fix vpi_release_handle to be called implicitly per IEEE (#2706).
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**** Fix vpi_release_handle to be called implicitly per IEEE (#2706).
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**** Fix tracing empty sc module (#2729).
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**** Fix tracing empty sc module (#2729).
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@ -773,9 +773,9 @@ void EmitCSyms::emitSymImp() {
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= dtypep->skipRefp(); // Skip AstRefDType/AstTypedef, or return same node
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= dtypep->skipRefp(); // Skip AstRefDType/AstTypedef, or return same node
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if (const AstNodeArrayDType* adtypep = VN_CAST(dtypep, NodeArrayDType)) {
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if (const AstNodeArrayDType* adtypep = VN_CAST(dtypep, NodeArrayDType)) {
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bounds += " ,";
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bounds += " ,";
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bounds += cvtToStr(adtypep->hi());
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bounds += cvtToStr(adtypep->left());
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bounds += ",";
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bounds += ",";
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bounds += cvtToStr(adtypep->lo());
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bounds += cvtToStr(adtypep->right());
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if (VN_IS(dtypep, PackArrayDType)) {
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if (VN_IS(dtypep, PackArrayDType)) {
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pdim++;
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pdim++;
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} else {
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} else {
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@ -327,6 +327,25 @@ int _mon_check_var() {
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CHECK_RESULT_CSTR(p, "vpiConstant");
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CHECK_RESULT_CSTR(p, "vpiConstant");
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}
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}
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TestVpiHandle vh5 = VPI_HANDLE("quads");
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CHECK_RESULT_NZ(vh5);
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{
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TestVpiHandle vh10 = vpi_handle(vpiLeftRange, vh5);
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CHECK_RESULT_NZ(vh10);
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vpi_get_value(vh10, &tmpValue);
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CHECK_RESULT(tmpValue.value.integer, 2);
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p = vpi_get_str(vpiType, vh10);
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CHECK_RESULT_CSTR(p, "vpiConstant");
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}
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{
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TestVpiHandle vh10 = vpi_handle(vpiRightRange, vh5);
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CHECK_RESULT_NZ(vh10);
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vpi_get_value(vh10, &tmpValue);
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CHECK_RESULT(tmpValue.value.integer, 3);
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p = vpi_get_str(vpiType, vh10);
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CHECK_RESULT_CSTR(p, "vpiConstant");
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}
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return 0;
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return 0;
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}
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}
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@ -29,7 +29,9 @@ extern "C" int mon_check();
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reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */;
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reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */;
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reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
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reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
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reg [61:0] quads[3:2] /*verilator public_flat_rw @(posedge clk) */;
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// verilator lint_off LITENDIAN
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reg [0:61] quads[2:3] /*verilator public_flat_rw @(posedge clk) */;
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// verilator lint_on LITENDIAN
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reg [31:0] count /*verilator public_flat_rd */;
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reg [31:0] count /*verilator public_flat_rd */;
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reg [31:0] half_count /*verilator public_flat_rd */;
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reg [31:0] half_count /*verilator public_flat_rd */;
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