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Support 'time'.

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This commit is contained in:
Wilson Snyder 2009-11-19 10:45:59 -05:00
parent 103bda04d9
commit 19d62b7a68
6 changed files with 18 additions and 9 deletions
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4
Changes
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@ -5,8 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.7**
** Support byte, shortint, int, longint, var and void in variables, parameters and
functions.
** Support byte, shortint, int, longint, time, var and void in variables,
parameters and functions.
** Support "program", "package", "import" and $unit.

2
bin/verilator
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@ -1706,7 +1706,7 @@ endcase, endfunction, endgenerate, endmodule, endspecify, endtask, final,
for, function, generate, genvar, if, initial, inout, input, int, integer,
localparam, logic, longint, macromodule, module, nand, negedge, nor, not,
or, output, parameter, posedge, reg, scalared, shortint, signed, supply0,
supply1, task, tri, typedef, var, vectored, while, wire, xnor, xor
supply1, task, time, tri, typedef, var, vectored, while, wire, xnor, xor
Generally supported.

7
src/V3Ast.h
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@ -224,13 +224,14 @@ public:
operator en () const { return m_e; }
int width() const {
switch (m_e) {
case BIT: return 1;
case BYTE: return 8;
case SHORTINT: return 16;
case INT: return 32;
case LONGINT: return 64;
case INTEGER: return 32;
case LOGIC: return 1;
case BIT: return 1;
case LONGINT: return 64;
case SHORTINT: return 16;
case TIME: return 64;
default: return 0;
}
}

2
src/verilog.l
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@ -240,6 +240,7 @@ escid \\[^ \t\f\r\n]+
"supply0" { FL; return ySUPPLY0; }
"supply1" { FL; return ySUPPLY1; }
"task" { FL; return yTASK; }
"time" { FL; return yTIME; }
"tri" { FL; return yTRI; }
"vectored" { FL; return yVECTORED; }
"while" { FL; return yWHILE; }
@ -290,7 +291,6 @@ escid \\[^ \t\f\r\n]+
"strong0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"strong1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"table" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"time" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"tran" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"tranif0" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }
"tranif1" { yyerrorf("Unsupported: Verilog 1995 reserved word not implemented: %s",yytext); }

3
src/verilog.y
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@ -309,6 +309,7 @@ class AstSenTree;
%token<fl> ySUPPLY0 "supply0"
%token<fl> ySUPPLY1 "supply1"
%token<fl> yTASK "task"
%token<fl> yTIME "time"
%token<fl> yTIMEPRECISION "timeprecision"
%token<fl> yTIMEUNIT "timeunit"
%token<fl> yTRI "tri"
@ -972,7 +973,7 @@ integer_atom_type<bdtypep>: // ==IEEE: integer_atom_type
| yINT { $$ = new AstBasicDType($1,AstBasicDTypeKwd::INT); }
| yLONGINT { $$ = new AstBasicDType($1,AstBasicDTypeKwd::LONGINT); }
| yINTEGER { $$ = new AstBasicDType($1,AstBasicDTypeKwd::INTEGER); }
//UNSUP yTIME { $$ = new AstBasicDType($1,AstBasicDTypeKwd::TIME); }
| yTIME { $$ = new AstBasicDType($1,AstBasicDTypeKwd::TIME); }
;
integer_vector_type<bdtypep>: // ==IEEE: integer_atom_type

9
test_regress/t/t_var_types.v
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@ -11,7 +11,7 @@ module t (/*AUTOARG*/);
int d_int;
longint d_longint;
integer d_integer;
//UNSUP time d_time;
time d_time;
// IEEE: integer_atom_type
bit d_bit;
@ -62,6 +62,7 @@ module t (/*AUTOARG*/);
function reg [1:0] f_reg2; f_reg2 = {96{1'b1}}; endfunction
function bit [1:0] f_bit2; f_bit2 = {96{1'b1}}; endfunction
function logic [1:0] f_logic2; f_logic2 = {96{1'b1}}; endfunction
function time f_time; f_time = {96{1'b1}}; endfunction
// verilator lint_on WIDTH
`define CHECK_ALL(name,bits,issigned,twostate) \
@ -82,6 +83,7 @@ module t (/*AUTOARG*/);
`CHECK_ALL(d_int ,32,1'b1,1'b1);
`CHECK_ALL(d_longint ,64,1'b1,1'b1);
`CHECK_ALL(d_integer ,32,1'b1,1'b0);
`CHECK_ALL(d_time ,64,1'b0,1'b1);
`CHECK_ALL(d_bit ,1 ,1'b0,1'b1);
`CHECK_ALL(d_logic ,1 ,1'b0,1'b0);
`CHECK_ALL(d_reg ,1 ,1'b0,1'b0);
@ -118,6 +120,7 @@ module t (/*AUTOARG*/);
`CHECK_F(f_int ,32);
`CHECK_F(f_longint ,64);
`CHECK_F(f_integer ,32);
`CHECK_F(f_time ,64);
`CHECK_F(f_bit ,1 );
`CHECK_F(f_logic ,1 );
`CHECK_F(f_reg ,1 );
@ -132,6 +135,10 @@ module t (/*AUTOARG*/);
d_longint = 2;
d_integer = 2;
// Special check
d_time = $time;
if ($time !== d_time) $stop;
$write("*-* All Finished *-*\n");
$finish;
end