Allow assert disable (#2168)

* Add +verilator+noassert flag

This allows to disable the assert check per simulation argument.

* Add AssertOn check for assert

Insert the check AssertOn to allow disabling of asserts.
Asserts can be disabled by not using the `--assert` flag or by calling
`AssertOn(false)`, or passing the "+verilator+noassert" runtime flag.
Add tests for this behavior.
Bad tests check that the assert still causes a stop.
Non bad tests check that asserts are properly disabled and cause no stop
of the simulation.

Fixes #2162.

Signed-off-by: Tobias Wölfel <tobias.woelfel@mailbox.org>

* Correct file location

Signed-off-by: Tobias Wölfel <tobias.woelfel@mailbox.org>

* Add description for single test execution

Without this description it is not obvious how to run a single test from
the regression test suite.

Signed-off-by: Tobias Wölfel <tobias.woelfel@mailbox.org>

Changes

@@ -5,6 +5,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 * Verilator 4.029 devel
 
+***   Add assertOn check for assert. [Tobias Wölfel]
+***   Add +verilator+noassert flag to disable assert checking. [Tobias Wölfel]
 
 * Verilator 4.028 2020-02-08
 

bin/verilator

@@ -421,6 +421,7 @@ more information.
      +verilator+prof+threads+window+I<value>   Set profile duration
      +verilator+rand+reset+I<value>    Set random reset technique
      +verilator+seed+I<value>          Set random seed
+     +verilator+noassert               Disable assert checking
      +verilator+V                      Verbose version and config
      +verilator+version                Show version and exit
 
@@ -1773,6 +1774,11 @@ For $random and "-x-initial unique", set the simulation runtime random seed
 value.  If zero or not specified picks a value from the system random
 number generator.
 
+=item +verilator+noassert
+
+Disable assert checking per runtime argument. This is the same as calling
+"Verilated::assertOn(false)" in the model.
+
 =item +verilator+V
 
 Shows the verbose version, including configuration information.

docs/CONTRIBUTORS

@@ -33,6 +33,7 @@ Richard Myers
 Sebastien Van Cauwenberghe
 Stefan Wallentowitz
 Tobias Rosenkranz
+Tobias Wölfel
 Todd Strader
 Wilson Snyder
 Yutetsu TAKATSUKASA

docs/internals.adoc

@@ -631,7 +631,7 @@ Test drivers are written in PERL. All invoke the main test driver script,
 which can provide detailed help on all the features available when writing
 a test driver.
 
-   test_regress/t/driver.pl --help
+   test_regress/driver.pl --help
 
 For convenience, a summary of the most commonly used features is provided
 here. All drivers require a call to `compile` subroutine to compile the
@@ -716,6 +716,13 @@ respectively 16,384 and 4,096. The method of doing this is system
 dependent, but on Fedora Linux it would require editing the
 `/etc/security/limits.conf` file as root.
 
+=== Manual Test Execution
+
+A specific regression test can be executed manually. To start the "EXAMPLE"
+test, run the following command.
+
+   test_regress/t/t_EXAMPLE.pl
+
 === Continuous Integration
 
 Verilator has a https://travis-ci.com/verilator/verilator[Travis CI environment]

include/verilated.cpp

@@ -2199,6 +2199,9 @@ void VerilatedImp::commandArgVl(const std::string& arg) {
         else if (commandArgVlValue(arg, "+verilator+seed+", value/*ref*/)) {
             Verilated::randSeed(atoi(value.c_str()));
         }
+        else if (arg == "+verilator+noassert") {
+            Verilated::assertOn(false);
+        }
         else if (arg == "+verilator+V") {
             versionDump();  // Someday more info too
             VL_FATAL_MT("COMMAND_LINE", 0, "",

src/V3Assert.cpp

@@ -150,7 +150,7 @@ private:
             // It's more LIKELY that we'll take the NULL if clause
             // than the sim-killing else clause:
             ifp->branchPred(VBranchPred::BP_LIKELY);
-            bodysp = ifp;
+            bodysp = newIfAssertOn(ifp);
         } else {
             nodep->v3fatalSrc("Unknown node type");
         }

test_regress/t/t_assert_disabled.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+top_filename("t/t_assert_on.v");
+
+compile();
+
+execute();
+
+ok(1);
+1;

test_regress/t/t_assert_enabled_bad.pl

@@ -0,0 +1,24 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(simulator => 1);
+
+top_filename("t/t_assert_on.v");
+
+compile(
+    verilator_flags2 => ['--assert'],
+    nc_flags2 => ['+assert'],
+    );
+
+execute(
+    fails => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_assert_enabled_off.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt => 1);
+
+top_filename("t/t_assert_on.v");
+
+compile(
+    verilator_flags2 => ["--assert"],
+    );
+
+execute(
+    all_run_flags => ["+verilator+noassert"],
+);
+
+ok(1);
+1;

test_regress/t/t_assert_enabled_on_bad.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+scenarios(vlt => 1);
+
+top_filename("t/t_assert_on.v");
+
+compile(
+    verilator_flags2 => ["--assert"],
+    );
+
+execute(
+    fails => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_assert_on.v

@@ -0,0 +1,18 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   always @ (posedge clk) begin
+      assert (0);
+      $finish;
+   end
+
+endmodule