Merge from master

test_regress/driver.pl

@@ -405,7 +405,6 @@ sub new {
 	ms_run_flags => [split(/\s+/,"-lib $self->{obj_dir}/work -c -do 'run -all;quit' ")],
 	# Verilator
 	vlt => 0,
-	'v3' => 0,
 	verilator_flags => ["-cc",
 			    "-Mdir $self->{obj_dir}",
 			    "-OD",  # As currently disabled unless -O3
@@ -419,6 +418,8 @@ sub new {
 	%$self};
     bless $self, $class;
 
+    $self->{vlt_all} = $self->{vlt};  # Any Verilator scenario
+
     $self->{VM_PREFIX} ||= "V".$self->{name};
     $self->{stats} ||= "$self->{obj_dir}/V".$self->{name}."__stats.txt";
     $self->{status_filename} ||= "$self->{obj_dir}/V".$self->{name}.".status";
@@ -557,6 +558,10 @@ sub _read_status {
     my $filename = $self->{status_filename};
     use vars qw($VAR1);
     local $VAR1;
+    if (!-r $filename) {
+        $self->error("driver.pl _read_status file missing: $filename");
+        return;
+    }
     require $filename or die "%Error: $! $filename,";
     if ($VAR1) {
 	%{$self} = %{$VAR1};
@@ -729,7 +734,7 @@ sub compile {
 		    fails=>$param{fails},
 		    cmd=>\@cmd);
     }
-    elsif ($param{vlt}) {
+    elsif ($param{vlt_all}) {
 	my @cmdargs = $self->compile_vlt_flags(%param);
 
 	if ($self->sc && !$self->have_sc) {
@@ -863,7 +868,7 @@ sub execute {
 		    expect=>$param{vcs_run_expect},	# non-verilator expect isn't the same
 		    );
     }
-    elsif ($param{vlt}
+    elsif ($param{vlt_all}
 	#&& (!$param{needs_v4} || -r "$ENV{VERILATOR_ROOT}/src/V3Gate.cpp")
 	) {
 	$param{executable} ||= "$self->{obj_dir}/$param{VM_PREFIX}";
@@ -887,7 +892,7 @@ sub execute {
 sub inline_checks {
     my $self = (ref $_[0]? shift : $Self);
     return 1 if $self->errors || $self->skips || $self->unsupporteds;
-    return 1 if !$self->{vlt};
+    return 1 if !$self->{vlt_all};
 
     my %param = (%{$self}, @_);	   # Default arguments are from $self
 

test_regress/t/t_alw_nosplit.pl

@@ -13,7 +13,7 @@ compile (
     verilator_flags2 => ["--stats"],
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep ($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0);
 }
 

test_regress/t/t_alw_split.pl

@@ -13,7 +13,7 @@ compile(
     verilator_flags2 => ["--stats"],
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep ($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 3);
 }
 

test_regress/t/t_alw_split_rst.pl

@@ -13,7 +13,7 @@ compile(
     verilator_flags2 => ["--stats"],
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep ($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0);
 }
 

test_regress/t/t_alw_splitord.pl

@@ -13,7 +13,7 @@ compile(
     verilator_flags2 => ["--stats"],
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep ($Self->{stats}, qr/Optimizations, Split always\s+(\d+)/i, 0);
 }
 

test_regress/t/t_array_packed_write_read.pl

@@ -8,8 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 scenarios(simulator => 1);
-
-$Self->{vlt} and unsupported("Verilator unsupported, bug446");
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug446");
 
 compile(
     );

test_regress/t/t_assert_basic_fail.pl

@@ -13,12 +13,13 @@ top_filename("t/t_assert_basic.v");
 
 compile(
     v_flags2 => ['+define+FAILING_ASSERTIONS',
-                 $Self->{vlt}?'--assert':($Self->{nc}?'+assert':'')],
+                 ($Self->{vlt_all} ? '--assert'
+                  : ($Self->{nc} ? '+assert' : ''))],
     fails => $Self->{nc},
     );
 
 execute(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     );
 
 ok(1);

test_regress/t/t_assert_elab_bad.pl

@@ -15,12 +15,12 @@ unlink("$Self->{obj_dir}/t_assert_elab_bad.log");
 
 compile(
     v_flags2 => ['+define+FAILING_ASSERTIONS',
-    $Self->{vlt}?'--assert':($Self->{nc}?'+assert':'')],
+    $Self->{vlt_all} ? '--assert' : ($Self->{nc} ? '+assert':'')],
     fails => 1,
 );
 
 execute(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
 );
 
 file_grep ("$Self->{obj_dir}/vlt_compile.log",

test_regress/t/t_assert_synth_full.pl

@@ -19,7 +19,7 @@ compile(
 
 execute(
     check_finished => 0,
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis full_case'
     );

test_regress/t/t_assert_synth_parallel.pl

@@ -19,7 +19,7 @@ compile(
 
 execute(
     check_finished => 0,
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t_assert_synth.v:\d+: Assertion failed in top.t: synthesis parallel_case'
     );

test_regress/t/t_case_huge.pl

@@ -13,7 +13,7 @@ compile(
     verilator_flags2 => ["--stats"],
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep ($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 10);
     file_grep ($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 8);
 }

test_regress/t/t_case_huge_prof.pl

@@ -15,10 +15,8 @@ compile(
     verilator_flags2 => ["--stats --profile-cfuncs -CFLAGS '-pg' -LDFLAGS '-pg'"],
     );
 
-if ($Self->{vlt}) {
-    file_grep ($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 10);
-    file_grep ($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 10);
-}
+file_grep ($Self->{stats}, qr/Optimizations, Tables created\s+(\d+)/i, 10);
+file_grep ($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 10);
 
 unlink $_ foreach (glob "$Self->{obj_dir}/gmon.out.*");
 $ENV{GMON_OUT_PREFIX} = "$Self->{obj_dir}/gmon.out";

test_regress/t/t_cellarray.pl

@@ -17,7 +17,7 @@ execute(
     check_finished => 1,
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep ($Self->{stats}, qr/Optimizations, Gate assign merged\s+(\d+)/i, 28);
 };
 

test_regress/t/t_clk_gater.pl

@@ -17,7 +17,7 @@ execute(
     check_finished => 1,
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     #Optimization is disabled
     #file_grep ($Self->{stats}, qr/Optimizations, Gaters inserted\s+(\d+)/i, 3);
 }

test_regress/t/t_clk_latch.pl

@@ -9,7 +9,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-my $fail = ($Self->{vlt} && verilator_version() !~ /\(ord\)/);
+my $fail = ($Self->{vlt_all} && verilator_version() !~ /\(ord\)/);
 
 compile(
     );

test_regress/t/t_clk_latch_edgestyle.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 top_filename("t/t_clk_latch.v");
 
-my $fail = ($Self->{vlt} && verilator_version() !~ /\(ord\)/);
+my $fail = ($Self->{vlt_all} && verilator_version() !~ /\(ord\)/);
 
 compile(
     v_flags2 => ['+define+EDGE_DETECT_STYLE'],

test_regress/t/t_cover_sva_notflat.pl

@@ -22,8 +22,9 @@ execute(
 # Allow old Perl format dump, or new binary dump
 # Check that the hierarchy doesn't include __PVT__
 # Otherwise our coverage reports would look really ugly
-file_grep ($Self->{coverage_filename}, qr/(top\.t\.sub.*.cyc_eq_5)/)
-    if $Self->{vlt};
+if ($Self->{vlt_all}) {
+    file_grep ($Self->{coverage_filename}, qr/(top\.t\.sub.*.cyc_eq_5)/)
+}
 
 ok(1);
 1;

test_regress/t/t_cover_toggle.pl

@@ -21,7 +21,7 @@ execute(
 inline_checks();
 
 file_grep ($Self->{stats}, qr/Coverage, Toggle points joined\s+(\d+)/i, 25)
-    if $Self->{vlt};
+    if $Self->{vlt_all};
 
 ok(1);
 1;

test_regress/t/t_debug_fatalsrc_bad.pl

@@ -11,7 +11,7 @@ scenarios(vlt => 1);
 
 compile(
     verilator_flags2 => ["--debug-fatalsrc"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: Internal Error: .*: --debug-fatal-src
 %Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.

test_regress/t/t_debug_fatalsrc_bt_bad.pl

@@ -12,7 +12,7 @@ $ENV{VERILATOR_TEST_NO_GDB} and skip("Skipping due to VERILATOR_TEST_NO_GDB");
 
 compile(
     v_flags2 => ["--lint-only --debug --gdbbt --debug-fatalsrc"],
-    fails => $Self->{vlt},
+    fails => 1,
     expect =>
 '%Error: Internal Error: .*: --debug-fatal-src
 %Error: Internal Error: See the manual and http://www.veripool.org/verilator for more assistance.

test_regress/t/t_debug_sigsegv_bad.pl

@@ -12,7 +12,7 @@ $ENV{VERILATOR_TEST_NO_GDB} and skip("Skipping due to VERILATOR_TEST_NO_GDB");
 
 compile(
     v_flags => ["--debug-sigsegv"],
-    fails => $Self->{vlt},
+    fails => 1,
     expect =>
 '%Error: Verilator internal fault, sorry.  Consider trying --debug --gdbbt
 %Error: Command Failed.*',

test_regress/t/t_debug_sigsegv_bt_bad.pl

@@ -12,7 +12,7 @@ $ENV{VERILATOR_TEST_NO_GDB} and skip("Skipping due to VERILATOR_TEST_NO_GDB");
 
 compile(
     v_flags2 => ["--lint-only --debug --gdbbt --debug-sigsegv"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '.*
 Program received signal SIGSEGV, Segmentation fault.

test_regress/t/t_dedupe_clk_gate.pl

@@ -13,7 +13,7 @@ compile(
     verilator_flags2 => ["--stats"],
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep ($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 4);
 }
 

test_regress/t/t_dedupe_seq_logic.pl

@@ -13,7 +13,7 @@ compile(
     verilator_flags2 => ["--stats"],
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep ($Self->{stats}, qr/Optimizations, Gate sigs deduped\s+(\d+)/i, 6);
 }
 

test_regress/t/t_dpi_2exp_bad.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_dpi_2exp_bad.v:11: Function was already DPI Exported, duplicate not allowed: dpix_twice
 %Error: Exiting due to .*'

test_regress/t/t_dpi_context_noopt.pl

@@ -13,7 +13,7 @@ top_filename("t/t_dpi_context.v");
 
 compile(
     v_flags2 => ["t/t_dpi_context_c.cpp"],
-    verilator_flags2 => [$Self->{vlt}?"-O0":""],
+    verilator_flags2 => [$Self->{vlt_all} ? "-O0" : ""],
     );
 
 execute(

test_regress/t/t_dpi_dup_bad.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_dpi_dup_bad.v:\d+: Duplicate declaration of DPI function with different formal arguments: t.oth_f_int2
 %Error: t/t_dpi_dup_bad.v:\d+: ... New prototype:      pure int dpii_fa_bit \(int, int\)

test_regress/t/t_dpi_exp_bad.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_dpi_exp_bad.v:\d+: DPI functions cannot return > 32 bits or four-state; use a two-state type or task instead: dpix_f_bit48__Vfuncrtn
 %Error: Exiting due to .*'

test_regress/t/t_dpi_logic_bad.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_dpi_logic_bad.v:\d+: DPI function may not return type BASICDTYPE \'logic\' \(IEEE 2017 35.5.5\)
 %Error: Exiting due to .*'

test_regress/t/t_dpi_name_bad.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_dpi_name_bad.v:\d+: DPI function has illegal characters in C identifier name: badly.named
 %Error: Exiting due to .*'

test_regress/t/t_dpi_openreg_bad.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_dpi_openreg_bad.v:\d+: Unsized/open arrays \(\'\[\]\'\) are only supported in DPI imports
 %Error: t/t_dpi_openreg_bad.v:\d+: Unsized/open arrays \(\'\[\]\'\) are only supported in DPI imports

test_regress/t/t_dpi_shortcircuit.pl

@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 scenarios(simulator => 1);
-$Self->{vlt} and unsupported("Verilator unsupported, bug413 short circuit");
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug413 short circuit");
 
 compile(
     # Amazingly VCS, NC and Verilator all just accept the C file here!

test_regress/t/t_enum_overlap_bad.pl

@@ -11,7 +11,7 @@ scenarios(vlt => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => 1,
     expect =>
 '%Error: t/t_enum_overlap_bad.v:\d+: Overlapping enumeration value: e1b
 %Error: t/t_enum_overlap_bad.v:\d+: ... Location of original declaration

test_regress/t/t_enum_public.pl

@@ -9,7 +9,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     compile(
         verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"],
         make_top_shell => 0,

test_regress/t/t_enum_type_pins.pl

@@ -9,7 +9,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 # Not yet working on Verilator
-$Self->{vlt} and unsupported("Verilator unsupported");
+$Self->{vlt_all} and unsupported("Verilator unsupported");
 
 compile(
     );

test_regress/t/t_enumeration.pl

@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 scenarios(simulator => 1);
-$Self->{vlt} and unsupported("Verilator unsupported, bug460");
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug460");
 
 compile(
     );

test_regress/t/t_flag_nomod_bad.pl

@@ -11,7 +11,7 @@ scenarios(vlt => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => 1,
     expect =>
 '%Error: No top level module found
 %Error: Exiting due to',

test_regress/t/t_flag_topmod2_bad.pl

@@ -11,8 +11,7 @@ scenarios(vlt => 1);
 
 compile(
     v_flags2 => ["--top-module a "],
-    fails => $Self->{vlt},
-    nc => 0,  # Need to get it not to give the prompt
+    fails => 1,
     expect =>
 '%Error: Specified --top-module \'a\' isn.t at the top level, it.s under another cell \'a_top\'
 %Error: Exiting due to.*',

test_regress/t/t_flag_topmodule_bad.pl

@@ -12,7 +12,7 @@ scenarios(vlt => 1);
 top_filename("t/t_flag_topmodule.v");
 
 compile(
-    fails => $Self->{vlt},
+    fails => 1,
     nc => 0,  # Need to get it not to give the prompt
     expect =>
 '%Error-MULTITOP: t/t_flag_topmodule.v:\d+: Unsupported: Multiple top level modules: .*

test_regress/t/t_flag_topmodule_bad2.pl

@@ -12,7 +12,7 @@ scenarios(vlt => 1);
 top_filename("t/t_flag_topmodule.v");
 
 compile(
-    fails => $Self->{vlt},
+    fails => 1,
     v_flags2 => ["--top-module notfound"],
     nc => 0,  # Need to get it not to give the prompt
     expect =>

test_regress/t/t_flag_werror_bad1.pl

@@ -13,7 +13,7 @@ top_filename("t/t_flag_werror.v");
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 q{%Warning-WIDTH: t/t_flag_werror.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST '6'h2e' generates 6 bits.
 %Warning-WIDTH: Use .* and lint_on around source to disable this message.

test_regress/t/t_flag_werror_bad2.pl

@@ -13,12 +13,12 @@ top_filename("t/t_flag_werror.v");
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => 1,
     verilator_flags => [qw(-cc -Werror-WIDTH)],
     expect =>
 q{%Error-WIDTH: t/t_flag_werror.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST '6'h2e' generates 6 bits.
 %Error: Exiting due to},
-    ) if $Self->{vlt};
+    );
 
 ok(1);
 1;

test_regress/t/t_func_bad2.pl

@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_func_bad2.v:\d+: Unsupported: Recursive function or task call
 %Error: Exiting due to',

test_regress/t/t_func_bad_width.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 q{%Warning-WIDTH: t/t_func_bad_width.v:\d+: Operator FUNCREF 'MUX' expects 40 bits on the Function Argument, but Function Argument's VARREF 'in' generates 39 bits.
 %Warning-WIDTH: Use [^\n]+

test_regress/t/t_func_public_trace.pl

@@ -9,7 +9,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-my $pubtask = ($Self->{vlt} && verilator_version() =~ /\(public_tasks\)/);  # TBD
+my $pubtask = ($Self->{vlt_all} && verilator_version() =~ /\(public_tasks\)/);  # TBD
 
 top_filename("t/t_func_public.v");
 

test_regress/t/t_genvar_misuse_bad.pl

@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 scenarios(simulator => 1);
-$Self->{vlt} and unsupported("Verilator unsupported, bug408");
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug408");
 
 compile(
     v_flags2 => ["--lint-only"],

test_regress/t/t_inst_overwide_bad.pl

@@ -16,7 +16,7 @@ compile(
     make_top_shell => 0,
     verilator_flags => [qw(-cc)],
     verilator_make_gcc => 0,
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 q{%Warning-WIDTH: t/t_inst_overwide.v:\d+: Output port connection 'outy_w92' expects 92 bits on the pin connection, but pin connection's VARREF 'outc_w30' generates 30 bits.
 %Warning-WIDTH: Use .* to disable this message.

test_regress/t/t_inst_tree_inl0_pub1.pl

@@ -35,7 +35,7 @@ sub checkRelativeRefs {
     }
 }
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     # We expect to combine sequent functions across multiple instances of
     # l2, l3, l4, l5. If this number drops, please confirm this has not broken.
     file_grep ($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 52);

test_regress/t/t_inst_tree_inl0_pub1_norelcfuncs.pl

@@ -15,7 +15,7 @@ compile(
     verilator_flags2 => ['+define+NOUSE_INLINE', '+define+USE_PUBLIC', '--stats', '--norelative-cfuncs'],
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     # Fewer optimizations than t_inst_tree_inl0_pub1 which allows
     # relative CFuncs:
     file_grep ($Self->{stats}, qr/Optimizations, Combined CFuncs\s+(\d+)/i, 31);

test_regress/t/t_interface_array_nocolon_bad.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 q{%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:\d+: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2
 %Warning-LITENDIAN: Use [^\n]+

test_regress/t/t_interface_down_gen.pl

@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 scenarios(simulator => 1);
-$Self->{vlt} and unsupported("Verilator unsupported, interface generates changing types");
+$Self->{vlt_all} and unsupported("Verilator unsupported, interface generates changing types");
 $Self->{vcs} and unsupported("Commercially unsupported, interface crossrefs");
 
 compile(

test_regress/t/t_interface_modport_export.pl

@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 scenarios(simulator => 1);
-$Self->{vlt} and unsupported("Verilator unsupported, bug696");
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug696");
 
 compile(
     );

test_regress/t/t_interface_param2.pl

@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 scenarios(simulator => 1);
-$Self->{vlt} and unsupported("Verilator unsupported, bug1104");
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug1104");
 
 compile(
     );

test_regress/t/t_lint_block_redecl_bad.pl

@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 scenarios(vlt_all => 1);
-$Self->{vlt} and unsupported("Verilator unsupported, bug485, false begin due to WHILE conversion blocks duplicate name detection");
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug485, false begin due to WHILE conversion blocks duplicate name detection");
 
 compile(
     v_flags2 => ["--lint-only"],

test_regress/t/t_mem_multi_ref_bad.pl

@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     nc => 0,  # Need to get it not to give the prompt
     expect =>
 q{%Error: t/t_mem_multi_ref_bad.v:\d+: Illegal bit or array select; type does not have a bit range, or bad dimension: type is (bit|logic)

test_regress/t/t_mem_shift.pl

@@ -13,7 +13,7 @@ compile(
     verilator_flags2 => ["--stats"],
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep ($Self->{stats}, qr/Optimizations, Delayed shared-sets\s+(\d+)/i, 14);
 }
 

test_regress/t/t_metacmt_onoff.pl

@@ -14,7 +14,7 @@ compile(
     verilator_make_gcc => 0,
     make_top_shell => 0,
     make_main => 0,
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Warning-LITENDIAN: t/t_metacmt_onoff.v:\d+: Little bit endian vector: MSB < LSB of bit range: 0:1
 %Warning-LITENDIAN: Use "/\* verilator lint_off LITENDIAN \*/" and lint_on around source to disable this message.

test_regress/t/t_order_clkinst.pl

@@ -9,7 +9,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-my $fail = ($Self->{vlt} && verilator_version() !~ /\(ord\)/);
+my $fail = ($Self->{vlt_all} && verilator_version() !~ /\(ord\)/);
 
 compile(
     );

test_regress/t/t_order_doubleloop.pl

@@ -9,7 +9,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-my $fail = ($Self->{vlt} && verilator_version() !~ /\(ord\)/);
+my $fail = ($Self->{vlt_all} && verilator_version() !~ /\(ord\)/);
 
 compile(
     );

test_regress/t/t_order_wireloop.pl

@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     # Used to be %Error: t/t_order_wireloop.v:\d+: Wire inputs its own output, creating circular logic .wire x=x.
     # However we no longer gate optimize this
     expect =>

test_regress/t/t_param_avec.pl

@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 scenarios(simulator => 1);
-$Self->{vlt} and unsupported("Verilator unsupported, bug477");
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug477");
 
 compile(
     );

test_regress/t/t_param_public.pl

@@ -9,7 +9,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 
 scenarios(simulator => 1);
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     compile(
         verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"],
         make_top_shell => 0,

test_regress/t/t_select_bad_range.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Warning-SELRANGE: t/t_select_bad_range.v:\d+: Selection index out of range: 44:44 outside 43:0
 %Warning-SELRANGE: Use .*

test_regress/t/t_select_bad_range2.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Warning-SELRANGE: t/t_select_bad_range2.v:\d+: Selection index out of range: 3:2 outside 1:0
 %Warning-SELRANGE: Use .*

test_regress/t/t_select_bad_range3.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Warning-SELRANGE: t/t_select_bad_range3.v:\d+: Selection index out of range: 13 outside 12:10
 %Warning-SELRANGE: Use .*

test_regress/t/t_select_bad_tri.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 q{%Error: t/t_select_bad_tri.v:\d+: Selection index is constantly unknown or tristated: lsb=7'bxxxxxxx width=32'sh47
 %Error: Exiting due to.*},

test_regress/t/t_struct_unpacked_bad.pl

@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 q{%Warning-UNPACKED: t/t_struct_unpacked_bad.v:\d+: Unsupported: Unpacked struct/union
 %Warning-UNPACKED: Use .*

test_regress/t/t_sv_bus_mux_demux.pl

@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 scenarios(simulator => 1);
-$Self->{vlt} and unsupported("Verilator unsupported, bug181");
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug181");
 
 compile(
     );

test_regress/t/t_sys_readmem_bad_addr.pl

@@ -13,7 +13,7 @@ compile(
     );
 
 execute(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_sys_readmem_bad_addr.mem:\d+: \$readmem file address beyond bounds of array',
     );

test_regress/t/t_sys_readmem_bad_digit.pl

@@ -13,7 +13,7 @@ compile(
     );
 
 execute(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_sys_readmem_bad_digit.mem:\d+: \$readmemb \(binary\) file contains hex characters',
     );

test_regress/t/t_sys_readmem_bad_end.pl

@@ -13,7 +13,7 @@ compile(
     );
 
 execute(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_sys_readmem_bad_end.mem:\d+: \$readmem file ended before specified ending-address',
     );

test_regress/t/t_sys_readmem_bad_notfound.pl

@@ -13,7 +13,7 @@ compile(
     );
 
 execute(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_sys_readmem_bad_NOTFOUND.mem:\d+: \$readmem file not found',
     );

test_regress/t/t_trace_ena_cc.pl

@@ -19,7 +19,7 @@ execute(
     check_finished => 1,
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep     ("$Self->{obj_dir}/V$Self->{name}__Trace__Slow.cpp", qr/c_trace_on\"/x);
     file_grep_not ("$Self->{obj_dir}/V$Self->{name}__Trace__Slow.cpp", qr/_trace_off\"/x);
     file_grep     ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);

test_regress/t/t_trace_ena_sc.pl

@@ -23,7 +23,7 @@ else {
         check_finished => 1,
         );
 
-    if ($Self->{vlt}) {
+    if ($Self->{vlt_all}) {
         # Note more checks in _cc.pl
         file_grep     ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
 

test_regress/t/t_trace_off_cc.pl

@@ -19,7 +19,7 @@ execute(
     check_finished => 1,
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     !-r "$Self->{obj_dir}/simx.vcd" or error("Tracing should be off\n");
 }
 

test_regress/t/t_trace_off_sc.pl

@@ -19,7 +19,7 @@ execute(
     check_finished => 1,
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     !-r "$Self->{obj_dir}/simx.vcd" or error("Tracing should be off\n");
 }
 

test_regress/t/t_trace_primitive.pl

@@ -17,7 +17,7 @@ execute(
     check_finished => 1,
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
    file_grep("$Self->{obj_dir}/simx.vcd", "sub_t_i");
 };
 

test_regress/t/t_tri_array.pl

@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 # When fix, update ifdefs in t_sv_cpu files; search for t_tri_array
-$Self->{vlt} and unsupported("Verilator unsupported, tristate arrays");
+$Self->{vlt_all} and unsupported("Verilator unsupported, tristate arrays");
 
 compile(
     );

test_regress/t/t_tri_pull2_bad.pl

@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_tri_pull2_bad.v:\d+: Unsupported: Conflicting pull directions.
 %Error: t/t_tri_pull2_bad.v:\d+: ... Location of conflicting pull.

test_regress/t/t_tri_pull_bad.pl

@@ -10,7 +10,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(simulator => 1);
 
 compile(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_tri_pull_bad.v:\d+: Unsupported: Conflicting pull directions.
 %Error: t/t_tri_pull_bad.v:\d+: ... Location of conflicting pull.

test_regress/t/t_tri_pullvec_bad.pl

@@ -11,7 +11,7 @@ scenarios(vlt_all => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_tri_pullvec_bad.v:\d+: Unsupported: Conflicting pull directions.
 %Error: t/t_tri_pullvec_bad.v:\d+: ... Location of conflicting pull.

test_regress/t/t_udp_bad.pl

@@ -12,14 +12,14 @@ scenarios(simulator => 1);
 top_filename("t/t_udp.v");
 
 compile(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_udp.v:\d+: Unsupported: Verilog 1995 UDP Tables.  Use --bbox-unsup to ignore tables.
 %Error: Exiting due to '
     );
 
 execute(
-    ) if !$Self->{vlt};
+    ) if !$Self->{vlt_all};
 
 ok(1);
 1;

test_regress/t/t_udp_noname.pl

@@ -8,7 +8,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 # Version 2.0.
 
 scenarios(simulator => 1);
-$Self->{vlt} and unsupported("Verilator unsupported, bug468");
+$Self->{vlt_all} and unsupported("Verilator unsupported, bug468");
 
 compile(
     );

test_regress/t/t_uniqueif_fail1.pl

@@ -19,7 +19,7 @@ compile(
     );
 
 execute(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
 %Error: t/t_uniqueif.v:\d+: Verilog \$stop

test_regress/t/t_uniqueif_fail2.pl

@@ -19,7 +19,7 @@ compile(
     );
 
 execute(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
 %Error: t/t_uniqueif.v:\d+: Verilog \$stop

test_regress/t/t_uniqueif_fail3.pl

@@ -19,7 +19,7 @@ compile(
     );
 
 execute(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
 %Error: t/t_uniqueif.v:\d+: Verilog \$stop

test_regress/t/t_uniqueif_fail4.pl

@@ -19,7 +19,7 @@ compile(
     );
 
 execute(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '.*%Error: t_uniqueif.v:\d+: Assertion failed in top.t: \'unique if\' statement violated
 %Error: t/t_uniqueif.v:\d+: Verilog \$stop

test_regress/t/t_unopt_combo_bad.pl

@@ -12,7 +12,7 @@ scenarios(simulator => 1);
 top_filename("t/t_unopt_combo.v");
 
 compile(
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Warning-UNOPTFLAT: t/t_unopt_combo.v:\d+: Signal unoptimizable: Feedback to clock or circular logic: t.c
 %Warning-UNOPTFLAT: Use "/\* verilator lint_off UNOPTFLAT \*/" and lint_on around source to disable this message.
@@ -25,7 +25,7 @@ compile(
     );
 
 execute(
-    ) if !$Self->{vlt};
+    ) if !$Self->{vlt_all};
 
 ok(1);
 1;

test_regress/t/t_unopt_combo_isolate.pl

@@ -15,7 +15,7 @@ compile(
     verilator_flags2 => ['+define+ISOLATE --stats'],
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep($Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+5/i);
 }
 

test_regress/t/t_unopt_converge_initial_run_bad.pl

@@ -18,7 +18,7 @@ compile(
 execute(
     fails => 1,
     expect => '%Error: \S+:\d+: Verilated model didn\'t DC converge',
-    ) if $Self->{vlt};
+    ) if $Self->{vlt_all};
 
 ok(1);
 1;

test_regress/t/t_unopt_converge_print_bad.pl

@@ -20,7 +20,7 @@ compile(
 execute(
     fails => 1,
     expect => '%Error: \S+:\d+: Verilated model didn\'t converge',
-    ) if $Self->{vlt};
+    ) if $Self->{vlt_all};
 
 ok(1);
 1;

test_regress/t/t_unopt_converge_run_bad.pl

@@ -18,7 +18,7 @@ compile(
 execute(
     fails => 1,
     expect => '%Error: \S+:\d+: Verilated model didn\'t converge',
-    ) if $Self->{vlt};
+    ) if $Self->{vlt_all};
 
 ok(1);
 1;

test_regress/t/t_var_bad_hide.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only -Wwarn-VARHIDDEN"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Warning-VARHIDDEN: t/t_var_bad_hide.v:\d+: Declaration of signal hides declaration in upper scope: top
 .*

test_regress/t/t_var_bad_hide2.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only -Wwarn-VARHIDDEN"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Warning-VARHIDDEN: t/t_var_bad_hide2.v:\d+: Declaration of signal hides declaration in upper scope: t
 %Warning-VARHIDDEN: t/t_var_bad_hide2.v:\d+: ... Location of original declaration

test_regress/t/t_var_bad_sv.pl

@@ -11,7 +11,7 @@ scenarios(simulator => 1);
 
 compile(
     v_flags2 => ["--lint-only"],
-    fails => $Self->{vlt},
+    fails => $Self->{vlt_all},
     expect =>
 '%Error: t/t_var_bad_sv.v:\d+: Unexpected "do": "do" is a SystemVerilog keyword misused as an identifier.
 %Error: t/t_var_bad_sv.v:\d+: Modify the Verilog-2001 code to avoid SV keywords, or use `begin_keywords or --language.

test_regress/t/t_var_escape.pl

@@ -11,14 +11,14 @@ scenarios(simulator => 1);
 
 compile(
     # Access is so we can dump waves
-    v_flags2 => [$Self->{vlt}?'-trace':' +access+rwc'],
+    v_flags2 => [$Self->{vlt_all} ? '-trace' : ' +access+rwc'],
     );
 
 execute(
     check_finished => 1,
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep     ("$Self->{obj_dir}/simx.vcd", qr/\$enddefinitions/x);
     my $sig = quotemeta("bra[ket]slash/dash-colon:9");
     file_grep     ("$Self->{obj_dir}/simx.vcd", qr/ $sig/);

test_regress/t/t_var_life.pl

@@ -13,7 +13,7 @@ compile(
     verilator_flags2 => ["--stats"],
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep($Self->{stats}, qr/Optimizations, Lifetime assign deletions\s+(\d+)/i, 4);
     file_grep($Self->{stats}, qr/Optimizations, Lifetime constant prop\s+(\d+)/i, 2);
 }

test_regress/t/t_var_nonamebegin.pl

@@ -26,7 +26,7 @@ t2 {mod}.tsk top.t
 *-* All Finished *-*'),
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     vcd_identical("$Self->{obj_dir}/simx.vcd",
                   "t/$Self->{name}.out");
 }

test_regress/t/t_var_pins_cc.pl

@@ -16,7 +16,7 @@ compile(
     verilator_make_gcc => 0,
     );
 
-if ($Self->{vlt}) {
+{
     file_grep ("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN8  \(i1,0,0\);/x);
     file_grep ("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN8  \(i8,7,0\);/x);
     file_grep ("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN16 \(i16,15,0\);/x);

test_regress/t/t_var_pins_sc1.pl

@@ -16,7 +16,7 @@ compile(
     make_main => 0,
     );
 
-if ($Self->{vlt}) {
+if ($Self->{vlt_all}) {
     file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in<sc_bv<1>\s> \s+ i1;/x);
     file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in<sc_bv<8>\s> \s+ i8;/x);
     file_grep ("$Self->{obj_dir}/$Self->{VM_PREFIX}.h", qr/sc_in<sc_bv<16>\s> \s+ i16;/x);