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Define VERILATOR in addition to verilator

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This commit is contained in:
Wilson Snyder 2010-01-14 19:22:12 -05:00
parent 8203c79f76
commit 16926edf18
7 changed files with 82 additions and 26 deletions
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10
bin/verilator
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@ -1450,12 +1450,14 @@ functions, the Verilog signals must be declared with /*verilator public*/.
See also the public task feature; writing a accessor may result in cleaner
code.
=item `VERILATOR
=item `verilator
=item `verilator3
The verilator and verilator3 defines are set by default so you may `ifdef
around compiler specific constructs.
The VERILATOR, verilator and verilator3 defines are set by default so you
may `ifdef around compiler specific constructs.
=item `verilog
@ -2549,9 +2551,9 @@ with '%' to see what lines Verilator believes need more coverage.
Translate on/off pragmas are generally a bad idea, as it's easy to have
mismatched pairs, and you can't see what another tool sees by just
preprocessing the code. Instead, use the preprocessor; Verilator defines
the "verilator" define for you, so just wrap the code in a ifndef region:
the "VERILATOR" define for you, so just wrap the code in a ifndef region:
`ifndef verilator
`ifndef VERILATOR
Something_Verilator_Dislikes;
`endif

1
src/V3PreShell.cpp
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@ -62,6 +62,7 @@ protected:
s_preprocp->debug(debug());
// Default defines
FileLine* prefl = new FileLine("INTERNAL_VERILATOR_DEFINE",0);
s_preprocp->defineCmdLine(prefl,"VERILATOR", "1"); // LEAK_OK
s_preprocp->defineCmdLine(prefl,"verilator", "1"); // LEAK_OK
s_preprocp->defineCmdLine(prefl,"verilator3", "1"); // LEAK_OK
s_preprocp->defineCmdLine(prefl,"systemc_clock", "/*verilator systemc_clock*/"); // LEAK_OK

4
test_regress/driver.pl
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@ -261,11 +261,11 @@ sub new {
ivrun_flags => [],
# VCS
vcs => 0,
vcs_flags => [split(/\s+/,"+cli -I +define+vcs+1 -q -sverilog -CFLAGS '-DVCS' ")],
vcs_flags => [split(/\s+/,"+cli -I +define+VCS+1 -q -sverilog -CFLAGS '-DVCS' ")],
vcs_flags2 => [], # Overridden in some sim files
# NC
nc => 0,
nc_flags => [split(/\s+/,"+licqueue +nowarn+LIBNOU +define+nc=1 -q +assert +sv -c")],
nc_flags => [split(/\s+/,"+licqueue +nowarn+LIBNOU +define+NC=1 -q +assert +sv -c ")],
nc_flags2 => [], # Overridden in some sim files
ncrun_flags => [split(/\s+/,"+licqueue -q +assert +sv -R")],
# Verilator

2
test_regress/t/t_display.v
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@ -42,7 +42,7 @@ module t;
multiline", $time);
// Str check
`ifndef nc // NC-Verilog 5.3 chokes on this test
`ifndef NC // NC-Verilog 5.3 chokes on this test
if (str !== 32'h00_bf_11_0a) $stop;
`endif
$write("*-* All Finished *-*\n");

77
test_regress/t/t_dpi_import.v
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@ -5,6 +5,16 @@
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR
`define NO_SHORTREAL
`endif
module t ();
// Allowed import return types:
@ -28,9 +38,13 @@ module t ();
import "DPI-C" pure function shortint dpii_f_shortint (input shortint i);
import "DPI-C" pure function longint dpii_f_longint (input longint i);
import "DPI-C" pure function chandle dpii_f_chandle (input chandle i);
//import "DPI-C" pure function real dpii_f_real (input real i);
//import "DPI-C" pure function shortreal dpii_f_shortreal (input shortreal i);
//import "DPI-C" pure function string dpii_f_string (input string i);
`ifndef VERILATOR
import "DPI-C" pure function string dpii_f_string (input string i);
import "DPI-C" pure function real dpii_f_real (input real i);
`endif
`ifndef NO_SHORTREAL
import "DPI-C" pure function shortreal dpii_f_shortreal(input shortreal i);
`endif
import "DPI-C" pure function void dpii_v_bit (input bit i, output bit o);
import "DPI-C" pure function void dpii_v_int (input int i, output int o);
@ -38,9 +52,13 @@ module t ();
import "DPI-C" pure function void dpii_v_shortint (input shortint i, output shortint o);
import "DPI-C" pure function void dpii_v_longint (input longint i, output longint o);
import "DPI-C" pure function void dpii_v_chandle (input chandle i, output chandle o);
//import "DPI-C" pure function void dpii_v_real (input real i, output real o);
//import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o);
//import "DPI-C" pure function void dpii_v_string (input string i, output string o);
`ifndef VERILATOR
import "DPI-C" pure function void dpii_v_string (input string i, output string o);
import "DPI-C" pure function void dpii_v_real (input real i, output real o);
`endif
`ifndef NO_SHORTREAL
import "DPI-C" pure function void dpii_v_shortreal(input shortreal i, output shortreal o);
`endif
import "DPI-C" function void dpii_f_void ();
@ -68,6 +86,13 @@ module t ();
shortint i_s, o_s;
longint i_l, o_l;
chandle i_c, o_c;
`ifndef VERILATOR
string i_n, o_n;
real i_g, o_g;
`endif
`ifndef NO_SHORTREAL
shortreal i_f, o_f;
`endif
bit [127:0] wide;
@ -103,19 +128,35 @@ module t ();
if (o_b33 !== ~i_b33) $stop;
if (o_b64 !== ~i_b64) $stop;
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_int (i_i) !== ~i_i) $stop;
if (dpii_f_byte (i_y) !== ~i_y) $stop;
if (dpii_f_shortint(i_s) !== ~i_s) $stop;
if (dpii_f_longint (i_l) !== ~i_l) $stop;
if (dpii_f_chandle (i_c) !== i_c) $stop;
if (dpii_f_bit (i_b) !== ~i_b) $stop;
if (dpii_f_int (i_i) !== ~i_i) $stop;
if (dpii_f_byte (i_y) !== ~i_y) $stop;
if (dpii_f_shortint (i_s) !== ~i_s) $stop;
if (dpii_f_longint (i_l) !== ~i_l) $stop;
if (dpii_f_chandle (i_c) !== i_c) $stop;
`ifndef VERILATOR
if (dpii_f_string (i_n) != i_n) $stop;
if (dpii_f_real (i_g) != i_g+1.5) $stop;
`endif
`ifndef NO_SHORTREAL
if (dpii_f_shortreal(i_f) != i_f+1.5) $stop;
`endif
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop;
dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop;
dpii_v_shortint(i_s,o_s); if (o_s !== ~i_s) $stop;
dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop;
dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop;
dpii_v_bit (i_b,o_b); if (o_b !== ~i_b) $stop;
dpii_v_int (i_i,o_i); if (o_i !== ~i_i) $stop;
dpii_v_byte (i_y,o_y); if (o_y !== ~i_y) $stop;
dpii_v_shortint (i_s,o_s); if (o_s !== ~i_s) $stop;
dpii_v_longint (i_l,o_l); if (o_l !== ~i_l) $stop;
dpii_v_chandle (i_c,o_c); if (o_c !== i_c) $stop;
`ifndef VERILATOR
`ifndef VCS // Strange link error
dpii_v_string (i_n,o_n); if (o_n != i_n) $stop;
`endif
dpii_v_real (i_g,o_g); if (o_g != i_g+1.5) $stop;
`endif
`ifndef NO_SHORTREAL
dpii_v_shortreal(i_f,o_f); if (o_f != i_f+1.5) $stop;
`endif
dpii_f_void();
dpii_t_void();

12
test_regress/t/t_dpi_import_c.cpp
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@ -44,6 +44,9 @@ extern "C" {
extern short int dpii_f_shortint(short int i);
extern long long dpii_f_longint (long long i);
extern void* dpii_f_chandle (void* i);
extern const char* dpii_f_string (const char* i);
extern double dpii_f_real (double i);
extern float dpii_f_shortreal(float i);
extern void dpii_v_bit (unsigned char i, unsigned char *o);
extern void dpii_v_int (int i, int *o);
@ -51,6 +54,9 @@ extern "C" {
extern void dpii_v_shortint (short int i, short int *o);
extern void dpii_v_longint (long long i, long long *o);
extern void dpii_v_chandle (void* i, void* *o);
extern void dpii_v_string (const char* i, const char** o);
extern void dpii_v_real (double i, double* o);
extern void dpii_v_shortreal(float i, float* o);
extern void dpii_f_void ();
extern int dpii_t_void ();
@ -77,6 +83,9 @@ char dpii_f_byte (char i) { return ~i; }
short int dpii_f_shortint(short int i) { return ~i; }
long long dpii_f_longint (long long i) { return ~i; }
void* dpii_f_chandle (void* i) { return i; }
const char* dpii_f_string (const char* i) { return i; }
double dpii_f_real (double i) { return i+1.5; }
float dpii_f_shortreal(float i) { return i+1.5; }
void dpii_v_bit (unsigned char i, unsigned char *o) { *o = SV_MASK(1) & ~i; }
void dpii_v_int (int i, int *o) { *o = ~i; }
@ -84,6 +93,9 @@ void dpii_v_byte (char i, char *o) { *o = ~i; }
void dpii_v_shortint (short int i, short int *o) { *o = ~i; }
void dpii_v_longint (long long i, long long *o) { *o = ~i; }
void dpii_v_chandle (void* i, void* *o) { *o = i; }
void dpii_v_string (const char* i, const char** o) { *o = i; }
void dpii_v_real (double i, double* o) { *o = i + 1.5; }
void dpii_v_shortreal(float i, float* o) { *o = i + 1.5; }
//======================================================================

2
test_regress/t/t_math_svl2.v
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@ -20,7 +20,7 @@ module t (/*AUTOARG*/
if ('1 !== {66{1'b1}}) $stop;
if ('x !== {66{1'bx}}) $stop;
if ('z !== {66{1'bz}}) $stop;
`ifndef nc // NC-Verilog 5.50-s09 chokes on this test
`ifndef NC // NC-Verilog 5.50-s09 chokes on this test
if ("\v" != 8'd11) $stop;
if ("\f" != 8'd12) $stop;
if ("\a" != 8'd7) $stop;