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Fix user-type parameter overlap (#5469)
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@ -348,7 +348,24 @@ class ParamProcessor final {
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if (dtypep->isRanged()) {
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key += "[" + cvtToStr(dtypep->left()) + ":" + cvtToStr(dtypep->right()) + "]";
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}
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} else if (const AstPackArrayDType* const dtypep = VN_CAST(nodep, PackArrayDType)) {
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key += "[";
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key += cvtToStr(dtypep->left());
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key += ":";
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key += cvtToStr(dtypep->right());
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key += "] ";
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key += paramValueString(dtypep->subDTypep());
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} else if (const AstInitArray* const initp = VN_CAST(nodep, InitArray)) {
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key += "{";
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for (auto it : initp->map()) {
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key += paramValueString(it.second->valuep());
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key += ",";
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}
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key += "}";
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} else if (const AstNodeDType* const dtypep = VN_CAST(nodep, NodeDType)) {
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key += dtypep->prettyDTypeName(true);
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}
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UASSERT_OBJ(!key.empty(), nodep, "Parameter yielded no value string");
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return key;
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}
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18
test_regress/t/t_interface_derived_type.py
Executable file
18
test_regress/t/t_interface_derived_type.py
Executable file
@ -0,0 +1,18 @@
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.compile()
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test.execute()
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test.passes()
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62
test_regress/t/t_interface_derived_type.v
Normal file
62
test_regress/t/t_interface_derived_type.v
Normal file
@ -0,0 +1,62 @@
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// DESCRIPTION: Verilator: SystemVerilog interface test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Iztok Jeras.
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// SPDX-License-Identifier: CC0-1.0
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interface intf #(
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parameter type data_t = bit,
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parameter int arr[2][4]
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) ();
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data_t data;
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// TODO -- some kind of issue with multi-dimensional array constness:
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// %Error: t/t_interface_derived_type.v:12:12: Expecting expression to be constant, but variable isn't const: 'arr'
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// : ... note: In instance 't.sub16'
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// 19 | logic [arr[0][0]-1:0] other_data;
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// | ^~~
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// `define SHOW_2D_BUG
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`ifdef SHOW_2D_BUG
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logic [arr[0][0]-1:0] other_data;
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`else
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logic [$bits(data)-1:0] other_data;
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`endif
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endinterface
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// finish report
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always @ (posedge clk) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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sub #(.width(8), .arr('{'{8, 2, 3, 4}, '{1, 2, 3, 4}})) sub8 ();
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sub #(.width(16), .arr('{'{16, 2, 3, 4}, '{1, 2, 3, 4}})) sub16 ();
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endmodule
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module sub #(
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parameter int width,
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parameter int arr[2][4]
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) ();
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typedef struct packed {
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logic [3:3] [0:0] [width-1:0] field;
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} user_type_t;
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intf #(
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.data_t(user_type_t),
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.arr(arr)
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) the_intf ();
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logic [width-1:0] signal;
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always_comb begin
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the_intf.data.field = signal;
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the_intf.other_data = signal;
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end
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endmodule
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