Fix logical not optimization with empty begin, #2291.

This commit is contained in:
Wilson Snyder 2020-04-28 21:15:20 -04:00
parent c6d1a9858a
commit 15ad3f46be
4 changed files with 45 additions and 1 deletions

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@ -38,6 +38,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix error on unpacked connecting to packed, #2288. [Joseph Shaker]
**** Fix logical not optimization with empty begin, #2291. [Baltazar Ortiz]
* Verilator 4.032 2020-04-04

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@ -1954,7 +1954,8 @@ private:
|| VN_IS(nodep->condp(), LogNot))
&& nodep->ifsp() && nodep->elsesp()) {
UINFO(4, "IF(NOT {x}) => IF(x) swapped if/else" << nodep << endl);
AstNode* condp = VN_CAST(nodep->condp(), Not)->lhsp()->unlinkFrBackWithNext();
AstNode* condp
= VN_CAST(nodep->condp(), NodeUniop)->lhsp()->unlinkFrBackWithNext();
AstNode* ifsp = nodep->ifsp()->unlinkFrBackWithNext();
AstNode* elsesp = nodep->elsesp()->unlinkFrBackWithNext();
AstIf* ifp = new AstIf(nodep->fileline(), condp, elsesp, ifsp);

17
test_regress/t/t_if_swap.pl Executable file
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@ -0,0 +1,17 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2019 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
ok(1);
1;

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@ -0,0 +1,24 @@
module t
(/*AUTOARG*/
// Inputs
clk
);
input clk;
integer f;
always @(posedge clk) begin
if (!$feof(f)) begin
$display("Doing stuff with file.");
end
// Commenting out these two lines fixes the fault
else begin
end
if (!$feof(f)) begin
end
else begin
$display("Not doing stuff with file.");
end
end
endmodule