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Tests: Complicated for loops long ago supported.
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@ -39,7 +39,6 @@ module t (/*AUTOARG*/
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for (g=16; g>=8; g--) always @(posedge clk) gen_post_MINUSMINUS[g] = 1'b1;
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for (g=8; g<=16; g+=2) always @(posedge clk) gen_PLUSEQ[g] = 1'b1;
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for (g=16; g>=8; g-=2) always @(posedge clk) gen_MINUSEQ[g] = 1'b1;
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`ifndef verilator //UNSUPPORTED
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for (g=8; g<=16; g*=2) always @(posedge clk) gen_TIMESEQ[g] = 1'b1;
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for (g=16; g>=8; g/=2) always @(posedge clk) gen_DIVEQ[g] = 1'b1;
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for (g=15; g>8; g%=8) always @(posedge clk) gen_MODEQ[g] = 1'b1;
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@ -49,7 +48,6 @@ module t (/*AUTOARG*/
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for (g=8; g<=16; g<<=2) always @(posedge clk) gen_SLEFTEQ[g] = 1'b1;
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for (g=16; g>=8; g>>=2) always @(posedge clk) gen_SRIGHTEQ[g] = 1'b1;
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for (g=16; g>=8; g>>>=2) always @(posedge clk) gen_SSRIGHTEQ[g] = 1'b1;
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`endif
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endgenerate
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always @ (posedge clk) begin
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@ -78,7 +76,6 @@ module t (/*AUTOARG*/
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if (gen_post_MINUSMINUS!== 32'b00000000000000011111111100000000) $stop;
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if (gen_PLUSEQ !== 32'b00000000000000010101010100000000) $stop;
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if (gen_MINUSEQ !== 32'b00000000000000010101010100000000) $stop;
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`ifndef verilator //UNSUPPORTED
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if (gen_TIMESEQ !== 32'b00000000000000010000000100000000) $stop;
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if (gen_DIVEQ !== 32'b00000000000000010000000100000000) $stop;
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if (gen_MODEQ !== 32'b00000000000000001000000000000000) $stop;
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@ -88,7 +85,6 @@ module t (/*AUTOARG*/
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if (gen_SLEFTEQ !== 32'b00000000000000000000000100000000) $stop;
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if (gen_SRIGHTEQ !== 32'b00000000000000010000000000000000) $stop;
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if (gen_SSRIGHTEQ !== 32'b00000000000000010000000000000000) $stop;
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`endif
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v=0; for (i=8; i<=16; ++i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
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v=0; for (i=16; i>=8; --i) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
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@ -96,7 +92,6 @@ module t (/*AUTOARG*/
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v=0; for (i=16; i>=8; i--) v[i] = 1'b1; if (v !== 32'b00000000000000011111111100000000) $stop;
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v=0; for (i=8; i<=16; i+=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop;
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v=0; for (i=16; i>=8; i-=2) v[i] = 1'b1; if (v !== 32'b00000000000000010101010100000000) $stop;
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`ifndef verilator //UNSUPPORTED
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v=0; for (i=8; i<=16; i*=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop;
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v=0; for (i=16; i>=8; i/=2) v[i] = 1'b1; if (v !== 32'b00000000000000010000000100000000) $stop;
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v=0; for (i=15; i>8; i%=8) v[i] = 1'b1; if (v !== 32'b00000000000000001000000000000000) $stop;
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@ -106,7 +101,6 @@ module t (/*AUTOARG*/
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v=0; for (i=8; i<=16; i<<=2) v[i] =1'b1; if (v !== 32'b00000000000000000000000100000000) $stop;
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v=0; for (i=16; i>=8; i>>=2) v[i] =1'b1; if (v !== 32'b00000000000000010000000000000000) $stop;
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v=0; for (i=16; i>=8; i>>>=2) v[i]=1'b1; if (v !== 32'b00000000000000010000000000000000) $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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@ -1,4 +1,4 @@
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// DESCRIPTION: Verilator: Unsupported tristate constructur error
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// DESCRIPTION: Verilator: Unsupported tristate construct error
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//
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// This is a compile only regression test of tristate handling for bug514
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//
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@ -1,4 +1,4 @@
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// DESCRIPTION: Verilator: Unsupported tristate constructur error
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// DESCRIPTION: Verilator: Unsupported tristate construct error
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//
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// This is a compile only regression test of tristate handling for bug514
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//
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