diff --git a/Changes b/Changes
index 8be0408bc..701761dbe 100644
--- a/Changes
+++ b/Changes
@@ -45,6 +45,7 @@ Verilator 5.021 devel
 * Fix tracing chandles (#4860). [Nathan Graybeal]
 * Fix $fwrite of null (#4862). [Jose Tejada]
 * Fix GCC tautological-compare warnings.
+* Fix compile error on structs with queues (and ignore toggle coverage on queues).
 
 
 Verilator 5.020 2024-01-01
diff --git a/src/V3Coverage.cpp b/src/V3Coverage.cpp
index 94266f79f..486fccc56 100644
--- a/src/V3Coverage.cpp
+++ b/src/V3Coverage.cpp
@@ -395,6 +395,8 @@ class CoverageVisitor final : public VNVisitor {
                     newent.cleanup();
                 }
             }
+        } else if (VN_IS(dtypep, QueueDType)) {
+            // Not covered
         } else {
             dtypep->v3fatalSrc("Unexpected node data type in toggle coverage generation: "
                                << dtypep->prettyTypeName());
diff --git a/src/V3EmitCBase.h b/src/V3EmitCBase.h
index 9042c12c1..efeb7a75f 100644
--- a/src/V3EmitCBase.h
+++ b/src/V3EmitCBase.h
@@ -70,10 +70,12 @@ public:
         return v3Global.opt.modPrefix() + "_" + VIdProtect::protect(nodep->name());
     }
     static bool isAnonOk(const AstVar* varp) {
+        AstNodeDType* const dtp = varp->dtypep()->skipRefp();
         return v3Global.opt.compLimitMembers() != 0  // Enabled
                && !varp->isStatic()  // Not a static variable
                && !varp->isSc()  // Aggregates can't be anon
-               && !VN_IS(varp->dtypep()->skipRefp(), SampleQueueDType)  // Aggregates can't be anon
+               && !VN_IS(dtp, SampleQueueDType)  // Aggregates can't be anon
+               && !(VN_IS(dtp, NodeUOrStructDType) && !VN_CAST(dtp, NodeUOrStructDType)->packed())
                && (varp->basicp() && !varp->basicp()->isOpaque());  // Aggregates can't be anon
     }
     static bool isConstPoolMod(const AstNode* modp) {
diff --git a/test_regress/t/t_cover_toggle.out b/test_regress/t/t_cover_toggle.out
index f7eacf7f4..df7d3b745 100644
--- a/test_regress/t/t_cover_toggle.out
+++ b/test_regress/t/t_cover_toggle.out
@@ -40,6 +40,11 @@
 %000000    wire [7:0] cyc_copy = cyc[7:0];
 %000002    wire       toggle_up;
         
+           typedef struct {
+              int q[$];
+           } str_queue_t;
+           str_queue_t str_queue;
+        
            alpha a1 (/*AUTOINST*/
                      // Outputs
                      .toggle_up                 (toggle_up),
@@ -71,7 +76,7 @@
            // CHECK_COVER_MISSING(-1)
         
            always @ (posedge clk) begin
-              if (cyc!=0) begin
+              if (cyc != 0) begin
                  cyc <= cyc + 1;
                  memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1;
                  toggle <= '0;
@@ -79,13 +84,15 @@
                  stoggle.b <= toggle;
                  utoggle.val1 <= real'(cyc[7:0]);
                  ptoggle[0][0] <= toggle;
-                 if (cyc==3) begin
+                 if (cyc == 3) begin
+                    str_queue.q.push_back(1);
                     toggle <= '1;
                  end
-                 if (cyc==4) begin
+                 if (cyc == 4) begin
+                    if (str_queue.q.size() != 1) $stop;
                     toggle <= '0;
                  end
-                 else if (cyc==10) begin
+                 else if (cyc == 10) begin
                     $write("*-* All Finished *-*\n");
                     $finish;
                  end
diff --git a/test_regress/t/t_cover_toggle.v b/test_regress/t/t_cover_toggle.v
index d5dd91bba..5cd37b0e3 100644
--- a/test_regress/t/t_cover_toggle.v
+++ b/test_regress/t/t_cover_toggle.v
@@ -39,6 +39,11 @@ module t (/*AUTOARG*/
    wire [7:0] cyc_copy = cyc[7:0];
    wire       toggle_up;
 
+   typedef struct {
+      int q[$];
+   } str_queue_t;
+   str_queue_t str_queue;
+
    alpha a1 (/*AUTOINST*/
              // Outputs
              .toggle_up                 (toggle_up),
@@ -70,7 +75,7 @@ module t (/*AUTOARG*/
    // CHECK_COVER_MISSING(-1)
 
    always @ (posedge clk) begin
-      if (cyc!=0) begin
+      if (cyc != 0) begin
          cyc <= cyc + 1;
          memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1;
          toggle <= '0;
@@ -78,13 +83,15 @@ module t (/*AUTOARG*/
          stoggle.b <= toggle;
          utoggle.val1 <= real'(cyc[7:0]);
          ptoggle[0][0] <= toggle;
-         if (cyc==3) begin
+         if (cyc == 3) begin
+            str_queue.q.push_back(1);
             toggle <= '1;
          end
-         if (cyc==4) begin
+         if (cyc == 4) begin
+            if (str_queue.q.size() != 1) $stop;
             toggle <= '0;
          end
-         else if (cyc==10) begin
+         else if (cyc == 10) begin
             $write("*-* All Finished *-*\n");
             $finish;
          end
diff --git a/test_regress/t/t_cover_toggle_points.out b/test_regress/t/t_cover_toggle_points.out
index 217fafa23..cdde942c8 100644
--- a/test_regress/t/t_cover_toggle_points.out
+++ b/test_regress/t/t_cover_toggle_points.out
@@ -60,6 +60,11 @@
 %000002    wire       toggle_up;
 -000002  point: comment=toggle_up
         
+           typedef struct {
+              int q[$];
+           } str_queue_t;
+           str_queue_t str_queue;
+        
            alpha a1 (/*AUTOINST*/
                      // Outputs
                      .toggle_up                 (toggle_up),
@@ -115,7 +120,7 @@
            // CHECK_COVER_MISSING(-1)
         
            always @ (posedge clk) begin
-              if (cyc!=0) begin
+              if (cyc != 0) begin
                  cyc <= cyc + 1;
                  memory[cyc + 'd100] <= memory[cyc + 'd100] + 2'b1;
                  toggle <= '0;
@@ -123,13 +128,15 @@
                  stoggle.b <= toggle;
                  utoggle.val1 <= real'(cyc[7:0]);
                  ptoggle[0][0] <= toggle;
-                 if (cyc==3) begin
+                 if (cyc == 3) begin
+                    str_queue.q.push_back(1);
                     toggle <= '1;
                  end
-                 if (cyc==4) begin
+                 if (cyc == 4) begin
+                    if (str_queue.q.size() != 1) $stop;
                     toggle <= '0;
                  end
-                 else if (cyc==10) begin
+                 else if (cyc == 10) begin
                     $write("*-* All Finished *-*\n");
                     $finish;
                  end
diff --git a/test_regress/t/t_gate_lvalue_const.v b/test_regress/t/t_gate_lvalue_const.v
index ac003d8f6..90082787a 100644
--- a/test_regress/t/t_gate_lvalue_const.v
+++ b/test_regress/t/t_gate_lvalue_const.v
@@ -52,7 +52,9 @@ module testMod
    (input wire [2:0] data_i);
 
    typedef logic [63:0]    time_t;
+   // verilator lint_off MULTIDRIVEN
    time_t [2:0] last_transition;
+   // verilator lint_on MULTIDRIVEN
    genvar b;
 
    generate