diff --git a/bin/verilator b/bin/verilator index 46aed1231..894ff3701 100755 --- a/bin/verilator +++ b/bin/verilator @@ -1116,10 +1116,25 @@ always @* to prevent these issues.) Verilator supports dotted references to variables, functions and tasks in different modules. However, references into named blocks and function-local -variables are not supported. References into generate statements and -arrayed instances are possible, but may use different names from the -Verilog standard; arrayed instances are named {cellName}__{instanceNumber}, -while for generates, it's genblk{instanceNumber} or genfor{loopCount}. +variables are not supported. References into arrayed and generated +instances work, but still require some work-arounds in the Verilog code: + +References into arrayed instances use different names from the Verilog +standard; arrayed instances are named {cellName}__{instanceNumber}. For +example a[2] is instead a__2. Thus you cannot use a parameter or variable +to select the index number; expand it into a case statement manually. + +References into generate statements also use different names from the +Verilog standard; the top level generate, any begin statement, and any +place where there is a implied begin statement (under each generate-if or +generate-case) adds a hierarchy level named genblkI. And +each generate-for adds genforI. The best bet is to comment out +the references and run with --debug and look in the at the _begin.tree +file, and see the hierarchy by looking at the names of all of the CELLs in +question. Replace __DOT__ with . in your program. For example most cells +under a for loop would be something like +"genblk__DOT__genfor0__DOT__I"; so use genblk.genfor0.I to +see inside that cell. =head2 Latches @@ -1354,6 +1369,9 @@ For significantly better performance, split this into 2 separate signals: wire [2:1] x_21 = x[1:0]; wire [0:0] x_0 = shift_in; +This warning may also be due to clock enables. To fix these, use the +clock_enable meta comment described above. + =item UNSIGNED Warns that you are comparing a unsigned value in a way that implies it is diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp index 17b2163a1..50e01911c 100644 --- a/src/V3Begin.cpp +++ b/src/V3Begin.cpp @@ -49,25 +49,6 @@ private: string m_beginScope; // Name of begin blocks above us //int debug() { return 9; } - bool nameMatchesGen(const char* namep, string& numr) { - numr = ""; - bool needbar = false; - for (const char* cp=namep; *cp; ) { - if (0==strncmp(cp,"genblk",6) || 0==strncmp(cp,"genfor",6)) { - cp += 6; - } else if (isdigit(*cp)) { - if (needbar) { numr += '_'; needbar = false; } - numr += *cp++; - } else if (*cp=='_') { - cp++; - needbar = true; - } else { - return false; // Not exact match - } - } - return true; - } - // VISITORS virtual void visit(AstModule* nodep, AstNUser*) { m_modp = nodep; @@ -84,15 +65,6 @@ private: UINFO(8," "<name().c_str(), nameNum/*ref*/) - // && 0) { // Messes up V3Link - // // Need to leave the dot or we mess up later V3LinkDot - // // gen[blk|for]##_gen[blk|for]## -> gen[blk|for]##__DOT__##... - // m_beginScope = oldScope + "__DOT__"+nameNum; - //UINFO(8,"nname "<name() + "__DOT__"; // So always found @@ -100,7 +72,7 @@ private: while ((pos=dottedname.find("__DOT__")) != string::npos) { string ident = dottedname.substr(0,pos); dottedname = dottedname.substr(pos+strlen("__DOT__")); - if (m_beginScope=="") m_beginScope = nodep->name(); + if (m_beginScope=="") m_beginScope = ident; else m_beginScope = m_beginScope + "__DOT__"+ident; // Create CellInline for dotted resolution AstCellInline* inlinep = new AstCellInline(nodep->fileline(), diff --git a/src/V3Param.cpp b/src/V3Param.cpp index 6345d8054..ebf4f08ac 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -127,10 +127,14 @@ private: nodep->iterateChildren(*this); // After expanding the generate, all statements under it can be moved // up, and the generate block deleted as it's not relevant - AstNode* stmtsp = nodep->stmtsp()->unlinkFrBackWithNext(); - nodep->replaceWith(stmtsp); + if (AstNode* stmtsp = nodep->stmtsp()) { + stmtsp->unlinkFrBackWithNext(); + nodep->replaceWith(stmtsp); + if (debug()>=9) stmtsp->dumpTree(cout,"-genout: "); + } else { + nodep->unlinkFrBack(); + } nodep->deleteTree(); nodep=NULL; - if (debug()>=9) stmtsp->dumpTree(cout,"-genout: "); } virtual void visit(AstGenIf* nodep, AstNUser*) { V3Width::widthParams(nodep); // Param typed widthing will NOT recurse the body diff --git a/src/verilog.y b/src/verilog.y index bd107d947..b6f2e1f2b 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -222,7 +222,7 @@ class AstSenTree; %type v2kPort ioDecl varDecl %type modParDecl modParList modParE %type modItem modItemList modItemListOrNone modOrGenItem -%type genItem genItemList genItemBegin genItemBlock genItemsBlock genCaseList +%type genItem genItemList genItemBegin genItemBlock genTopBlock genCaseList %type dterm %type onesig sigId sigIdRange paramId sigList regsig regsigList regSigId %type netSig netSigList @@ -399,7 +399,7 @@ modItemList: modItem { $$ = $1; } ; modItem: modOrGenItem { $$ = $1; } - | yGENERATE genItemsBlock yENDGENERATE { $$ = new AstGenerate($1, $2); } + | yGENERATE genTopBlock yENDGENERATE { $$ = new AstGenerate($1, $2); } | ySCHDR { $$ = new AstScHdr(CRELINE(),*$1); } | ySCINT { $$ = new AstScInt(CRELINE(),*$1); } | ySCIMP { $$ = new AstScImp(CRELINE(),*$1); } @@ -437,7 +437,7 @@ genItemBlock: genItem { $$ = new AstBegin(CRELINE(),"genblk",$1); } | genItemBegin { $$ = $1; } ; -genItemsBlock: genItemList { $$ = new AstBegin(CRELINE(),"genblk",$1); } +genTopBlock: genItemList { $$ = new AstBegin(CRELINE(),"genblk",$1); } | genItemBegin { $$ = $1; } ;