diff --git a/test_regress/t/t_type_param.v b/test_regress/t/t_type_param.v index 7b56d596c..0193bde41 100644 --- a/test_regress/t/t_type_param.v +++ b/test_regress/t/t_type_param.v @@ -5,22 +5,54 @@ module foo #( parameter type bar = logic) - (); + (output int bar_size); localparam baz = $bits(bar); + + assign bar_size = baz; endmodule module t(); - logic [7:0] qux; + logic [7:0] qux1; + int bar_size1; - foo #(.bar (logic [ $bits(qux) - 1 : 0])) foo_inst (); -// initial begin + foo #(.bar (logic [ $bits(qux1) - 1 : 0])) + foo_inst1 (.bar_size (bar_size1)); + + logic [7:0] qux2; + int bar_size2; + + foo #(.bar (logic [ $bits(qux2) - 1 : 0])) + foo_inst2 (.bar_size (bar_size2)); + + logic [7:0] qux3; + int bar_size3; + + foo #(.bar (logic [ $bits(qux3) - 1 : 0])) + foo_inst3 (.bar_size (bar_size3)); + + initial begin // if ($bits(qux) != $bits(foo_inst.baz)) begin -// $display("%m: m != bits of foo_inst.baz (%0d, %0d)", +// $display("%m: bits of qux != bits of foo_inst.baz (%0d, %0d)", // $bits(qux), $bits(foo_inst.baz)); // $stop(); // end -// end + if (bar_size1 != $bits(qux1)) begin + $display("%m: bar_size1 != bits of qux1 (%0d, %0d)", + bar_size1, $bits(qux1)); + $stop(); + end + if (bar_size2 != $bits(qux2)) begin + $display("%m: bar_size2 != bits of qux2 (%0d, %0d)", + bar_size2, $bits(qux2)); + $stop(); + end + if (bar_size3 != $bits(qux3)) begin + $display("%m: bar_size3 != bits of qux3 (%0d, %0d)", + bar_size3, $bits(qux3)); + $stop(); + end + end genvar m; generate @@ -33,7 +65,7 @@ module t(); // end // end - foo #(.bar (logic[m-1:0])) foo_inst (); + foo #(.bar (logic[m-1:0])) foo_inst (.bar_size ()); end endgenerate diff --git a/test_regress/t/t_type_param_collision.pl b/test_regress/t/t_type_param_collision.pl new file mode 100755 index 000000000..6d50174d7 --- /dev/null +++ b/test_regress/t/t_type_param_collision.pl @@ -0,0 +1,23 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Todd Strader. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(simulator => 1); + +top_filename("t/t_type_param.v"); + +compile( + verilator_flags2 => ["--debug-collision"] + ); + +execute( + check_finished => 1, + ); + +ok(1); +1;