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Fix __Vlip undefined error in --freloop (#4824).
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@ -20,6 +20,7 @@ Verilator 5.023 devel
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**Minor:**
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* Fix invalid cast on string structure creation (#4921). [esynr3z]
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* Fix __Vlip undefined error in --freloop (#4824). [Justin Yao Du]
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Verilator 5.022 2024-02-24
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@ -41,7 +41,7 @@ VL_DEFINE_DEBUG_FUNCTIONS;
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class ReloopVisitor final : public VNVisitor {
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// NODE STATE
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// AstCFunc::user1p -> Var* for temp var, 0=not set yet
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// AstCFunc::user1p -> Var number temp var, 0=not set yet
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const VNUser1InUse m_inuser1;
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// STATE
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@ -63,18 +63,11 @@ class ReloopVisitor final : public VNVisitor {
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// METHODS
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static AstVar* findCreateVarTemp(FileLine* fl, AstCFunc* cfuncp) {
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AstVar* varp = VN_AS(cfuncp->user1p(), Var);
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if (!varp) {
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const string newvarname{"__Vilp"};
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varp = new AstVar{fl, VVarType::STMTTEMP, newvarname, VFlagLogicPacked{}, 32};
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UASSERT_OBJ(cfuncp, fl, "Assignment not under a function");
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if (cfuncp->initsp())
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cfuncp->initsp()->addNextHere(varp);
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else
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cfuncp->addInitsp(varp);
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cfuncp->user1p(varp);
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}
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static AstVar* createVarTemp(FileLine* fl, AstCFunc* cfuncp) {
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UASSERT_OBJ(cfuncp, fl, "Assignment not under a function");
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const string newvarname{"__Vilp" + std::to_string(cfuncp->user1Inc() + 1)};
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AstVar* const varp
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= new AstVar{fl, VVarType::STMTTEMP, newvarname, VFlagLogicPacked{}, 32};
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return varp;
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}
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void mergeEnd() {
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@ -93,7 +86,7 @@ class ReloopVisitor final : public VNVisitor {
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AstNodeAssign* const bodyp = m_mgAssignps.front();
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UASSERT_OBJ(bodyp->lhsp() == m_mgSelLp, bodyp, "Corrupt queue/state");
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FileLine* const fl = bodyp->fileline();
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AstVar* const itp = findCreateVarTemp(fl, m_mgCfuncp);
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AstVar* const itp = createVarTemp(fl, m_mgCfuncp);
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if (m_mgOffset > 0) {
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UASSERT_OBJ(m_mgIndexLo >= m_mgOffset, bodyp,
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@ -111,7 +104,8 @@ class ReloopVisitor final : public VNVisitor {
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new AstAdd{fl, new AstConst{fl, 1}, new AstVarRef{fl, itp, VAccess::READ}}};
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AstWhile* const whilep = new AstWhile{fl, condp, nullptr, incp};
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initp->addNext(whilep);
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bodyp->replaceWith(initp);
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itp->AstNode::addNext(initp);
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bodyp->replaceWith(itp);
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whilep->addStmtsp(bodyp);
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// Replace constant index with new loop index
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22
test_regress/t/t_reloop_local.pl
Executable file
22
test_regress/t/t_reloop_local.pl
Executable file
@ -0,0 +1,22 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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verilator_flags2 => ['--assert'],
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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88
test_regress/t/t_reloop_local.v
Normal file
88
test_regress/t/t_reloop_local.v
Normal file
@ -0,0 +1,88 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Justin Yao Du.
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// SPDX-License-Identifier: CC0-1.0
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typedef logic [7:0] Word;
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typedef logic [255:0] BigItem;
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module shuffler
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(
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input logic clk,
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input logic reset_l,
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output logic odd,
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output logic [255:0][7:0] shuffle
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);
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Word ctr;
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assign odd = ctr[0];
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always_ff @(posedge clk) begin
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if (!reset_l) begin
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ctr <= 0;
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end
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else begin
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ctr <= ctr + 1;
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end
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end
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for (genvar i = 0; i < 256; i++) always_comb begin
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shuffle[i] = Word'(i) - ctr;
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end
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for (genvar i = 0; i < 256; i++) begin
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assert property (@(posedge clk) shuffle[ctr + Word'(i)] == i);
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end
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endmodule
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interface big_port();
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BigItem big;
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function automatic BigItem get_big();
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return big;
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endfunction
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modport reader(import get_big);
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endinterface
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module foo (
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input clk,
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input reset_l,
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big_port.reader big);
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logic odd;
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Word[255 : 0] shuffle;
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shuffler fifo (
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.clk,
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.reset_l,
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.odd,
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.shuffle
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);
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BigItem bigs[256];
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for (genvar i = 0; i < 256; i++) always_comb begin
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bigs[i] = odd ? big.get_big() : 0;
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end
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endmodule
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module t (/*AUTOARG*/
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// Inputs
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clk, reset_l
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);
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input clk;
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input reset_l;
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big_port big();
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foo foo (
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.clk,
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.reset_l,
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.big);
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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