diff --git a/src/V3PreLex.l b/src/V3PreLex.l
index e32ee7c0c..bb591ba9e 100644
--- a/src/V3PreLex.l
+++ b/src/V3PreLex.l
@@ -159,7 +159,7 @@ bom             [\357\273\277]
                           LEXP->curFilelinep()->v3warn(PROTECTED, "A '`pragma protected data_block' encrypted section was detected and will be skipped.");
                           BEGIN(ENCBASE64);
                           return VP_TEXT; }
-<PRAGMAPRT>("begin_protected"|"end_protected")[\n\r]  { FL_FWDC; linenoInc(); BEGIN(INITIAL); return VP_TEXT; }
+<PRAGMAPRT>("begin_protected"|"end_protected"|"end")[\n\r]  { FL_FWDC; linenoInc(); BEGIN(INITIAL); return VP_TEXT; }
 <PRAGMAPRT>"version="[^\n\r]*[\n\r] {
                           FL_FWDC;
                           linenoInc();
@@ -175,6 +175,10 @@ bom             [\357\273\277]
                           linenoInc();
                           BEGIN(INITIAL);
                           return VP_TEXT; }
+    /* end of `pragma protect */
+<PRAGMAPRT>{wsn}+        { FL_FWDC; return VP_TEXT; }
+<PRAGMAPRT>[\n\r]        { FL_FWDC; linenoInc(); BEGIN(INITIAL); return VP_TEXT; }
+
     /* catch-all for unknown '`pragma protect' rules */
 <PRAGMAPRT>.            { yyless(0);
                           BEGIN(PRAGMAPRTERR);
@@ -202,7 +206,7 @@ bom             [\357\273\277]
 
     /* Catch only empty `pragma lines */
 <INITIAL>"`pragma"{wsn}*[\n\r]  {
-                          yyless(yyleng-1); FL_FWDC;
+                          yyless(yyleng - 1); FL_FWDC;
                           if (v3Global.opt.pedantic()) {
                               LEXP->curFilelinep()->v3warn(BADSTDPRAGMA, "`pragma is missing a pragma_expression.");
                           }
@@ -210,12 +214,11 @@ bom             [\357\273\277]
 
     /* catch all other nonempty `pragma */
 <INITIAL>"`pragma"{wsn}*[^\n\r]  {
-                          yyless(yyleng-1); FL_FWDC;
+                          yyless(yyleng - 1); FL_FWDC;
                           if (!v3Global.opt.preprocOnly())
                               BEGIN(PRAGMA);
                           return VP_TEXT; }
 <PRAGMA>"protect"{wsn}* { FL_FWDC; BEGIN(PRAGMAPRT); return VP_TEXT;}
-
     /* catch-all for unknown `pragma rules */
 <PRAGMA>.               { yyless(0);
                           BEGIN(PRAGMAERR);
diff --git a/src/verilog.y b/src/verilog.y
index 21015f440..a5ec944e3 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -4779,7 +4779,7 @@ gateUnsupPinList<nodep>:
 	;
 
 gatePinExpr<nodep>:
-		expr					{ $$ = GRAMMARP ->createGatePin($1); }
+		expr					{ $$ = GRAMMARP->createGatePin($1); }
 	;
 
 // This list is also hardcoded in VParseLex.l
diff --git a/test_regress/t/t_preproc.out b/test_regress/t/t_preproc.out
index 376c8eb4b..d3d6e5c83 100644
--- a/test_regress/t/t_preproc.out
+++ b/test_regress/t/t_preproc.out
@@ -325,9 +325,14 @@ ZCBXb3JrIGFzIG==
 `pragma protect end_protected
 
 `line 211 "t/t_preproc.v" 0
+ 
+`pragma protect
+`pragma protect end
+
+`line 215 "t/t_preproc.v" 0
 endmodule
 
-`line 213 "t/t_preproc.v" 0
+`line 217 "t/t_preproc.v" 0
  
  
  
@@ -338,17 +343,17 @@ endmodule
  
  
 
-`line 223 "t/t_preproc.v" 0
+`line 227 "t/t_preproc.v" 0
 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
 begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
 begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end  more
 
-`line 227 "t/t_preproc.v" 0
+`line 231 "t/t_preproc.v" 0
  
  
  
  
-`line 230 "t/t_preproc.v" 0
+`line 234 "t/t_preproc.v" 0
 `line 1 "t/t_preproc_inc4.vh" 1
  
 `line 2 "t/t_preproc_inc4.vh" 0
@@ -360,57 +365,57 @@ begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end  more
  
 
 `line 8 "t/t_preproc_inc4.vh" 2
-`line 230 "t/t_preproc.v" 0
-
-`line 231 "t/t_preproc.v" 0
- 
-  
-
 `line 234 "t/t_preproc.v" 0
- 
 
-`line 236 "t/t_preproc.v" 0
+`line 235 "t/t_preproc.v" 0
  
   
 
+`line 238 "t/t_preproc.v" 0
+ 
 
 `line 240 "t/t_preproc.v" 0
  
+  
+
+
+`line 244 "t/t_preproc.v" 0
+ 
  
 
-`line 243 "t/t_preproc.v" 0
+`line 247 "t/t_preproc.v" 0
  
 $blah("ab,cd","e,f");
 $blah(this.logfile,vec);
 $blah(this.logfile,vec[1,2,3]);
 $blah(this.logfile,{blah.name(), " is not foo"});
 
-`line 249 "t/t_preproc.v" 0
+`line 253 "t/t_preproc.v" 0
  
  
 
-`line 252 "t/t_preproc.v" 0
+`line 256 "t/t_preproc.v" 0
 `pragma foo = 1
 `default_nettype none
 `default_nettype uwire
 
-`line 256 "t/t_preproc.v" 0
+`line 260 "t/t_preproc.v" 0
  
  
 
-`line 259 "t/t_preproc.v" 0
+`line 263 "t/t_preproc.v" 0
  
  
    
 
-`line 263 "t/t_preproc.v" 0
-Line_Preproc_Check 263
+`line 267 "t/t_preproc.v" 0
+Line_Preproc_Check 267
 
-`line 265 "t/t_preproc.v" 0
+`line 269 "t/t_preproc.v" 0
  
  
 
-`line 268 "t/t_preproc.v" 0
+`line 272 "t/t_preproc.v" 0
     
 
 
@@ -418,15 +423,15 @@ Line_Preproc_Check 263
 
 
 
-`line 275 "t/t_preproc.v" 0
+`line 279 "t/t_preproc.v" 0
 (x,y)
-Line_Preproc_Check 276
+Line_Preproc_Check 280
 
-`line 278 "t/t_preproc.v" 0
+`line 282 "t/t_preproc.v" 0
  
  
 
-`line 281 "t/t_preproc.v" 0
+`line 285 "t/t_preproc.v" 0
  
  
  
@@ -435,17 +440,17 @@ beginend
 beginend     
 "beginend"   
 
-`line 289 "t/t_preproc.v" 0
+`line 293 "t/t_preproc.v" 0
  
  
  
  
   `\esc`def
 
-`line 295 "t/t_preproc.v" 0
+`line 299 "t/t_preproc.v" 0
 Not a \`define
 
-`line 297 "t/t_preproc.v" 0
+`line 301 "t/t_preproc.v" 0
  
  
  
@@ -454,23 +459,23 @@ Not a \`define
  
 x,y)--bee  submacro has comma paren
 
-`line 305 "t/t_preproc.v" 0
+`line 309 "t/t_preproc.v" 0
  
  
  
 $display("10 %d %d", $bits(foo), 10);
 
-`line 310 "t/t_preproc.v" 0
+`line 314 "t/t_preproc.v" 0
  
  
  
     
 
-`line 315 "t/t_preproc.v" 0
+`line 319 "t/t_preproc.v" 0
     
     
 
-`line 318 "t/t_preproc.v" 0
+`line 322 "t/t_preproc.v" 0
  
  
  
@@ -485,30 +490,30 @@ $display("10 %d %d", $bits(foo), 10);
 
 
 
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
 
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
    							
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
          	
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
       
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
 					
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
   								
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
      					
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
           		
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
     							
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
      assign a3 = ~b3 ;						
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
   
 
-`line 334 "t/t_preproc.v" 0
+`line 338 "t/t_preproc.v" 0
  
  	\
  
@@ -519,56 +524,56 @@ $display("10 %d %d", $bits(foo), 10);
 
 
 
-`line 343 "t/t_preproc.v" 0
+`line 347 "t/t_preproc.v" 0
    
-`line 343 "t/t_preproc.v" 0
+`line 347 "t/t_preproc.v" 0
  		
-`line 343 "t/t_preproc.v" 0
+`line 347 "t/t_preproc.v" 0
    def i		
 
 
-`line 345 "t/t_preproc.v" 0
+`line 349 "t/t_preproc.v" 0
  
 
-`line 347 "t/t_preproc.v" 0
- 
- 
- 
-
-
 `line 351 "t/t_preproc.v" 0
  
+ 
+ 
+
+
+`line 355 "t/t_preproc.v" 0
+ 
 
  
 
 
 
-`line 357 "t/t_preproc.v" 0
+`line 361 "t/t_preproc.v" 0
 1 /*verilator NOT IN DEFINE*/  (nodef)
 2 /*verilator PART OF DEFINE*/  (hasdef)
 3 
-`line 359 "t/t_preproc.v" 0
+`line 363 "t/t_preproc.v" 0
 /*verilator NOT PART
  OF DEFINE*/  (nodef)
-`line 360 "t/t_preproc.v" 0
+`line 364 "t/t_preproc.v" 0
 4 
-`line 360 "t/t_preproc.v" 0
+`line 364 "t/t_preproc.v" 0
 /*verilator PART 
  OF DEFINE*/  (nodef)
-`line 361 "t/t_preproc.v" 0
+`line 365 "t/t_preproc.v" 0
 5 also in  
-`line 361 "t/t_preproc.v" 0
+`line 365 "t/t_preproc.v" 0
   also3 (nodef)
  
 
 HAS a NEW 
-`line 364 "t/t_preproc.v" 0
+`line 368 "t/t_preproc.v" 0
 LINE
 
-`line 366 "t/t_preproc.v" 0
+`line 370 "t/t_preproc.v" 0
  
 
-`line 368 "t/t_preproc.v" 0
+`line 372 "t/t_preproc.v" 0
  
 
 
@@ -582,11 +587,11 @@ LINE
 
 
 
-`line 381 "t/t_preproc.v" 0
+`line 385 "t/t_preproc.v" 0
  
  
 
-`line 384 "t/t_preproc.v" 0
+`line 388 "t/t_preproc.v" 0
 EXP: clxx_scen
 clxx_scen
 EXP: clxx_scen
@@ -594,44 +599,44 @@ EXP: clxx_scen
  
 EXP: do if (start("verilog/inc1.v", 25)) begin  message({"Blah-", "clx_scen", " end"}); end  while(0);
 
-`line 390 "t/t_preproc.v" 0
+`line 394 "t/t_preproc.v" 0
    do 
-`line 390 "t/t_preproc.v" 0
+`line 394 "t/t_preproc.v" 0
         
-`line 390 "t/t_preproc.v" 0
+`line 394 "t/t_preproc.v" 0
   
-`line 390 "t/t_preproc.v" 0
+`line 394 "t/t_preproc.v" 0
     
-`line 390 "t/t_preproc.v" 0
- 
-`line 390 "t/t_preproc.v" 0
-      if (start("t/t_preproc.v", 390)) begin 
-`line 390 "t/t_preproc.v" 0
- 
-`line 390 "t/t_preproc.v" 0
-	 message({"Blah-", "clx_scen", " end"}); 
-`line 390 "t/t_preproc.v" 0
-      end 
-`line 390 "t/t_preproc.v" 0
-        
-`line 390 "t/t_preproc.v" 0
-   while(0);
-
-`line 392 "t/t_preproc.v" 0
- 
-
 `line 394 "t/t_preproc.v" 0
  
+`line 394 "t/t_preproc.v" 0
+      if (start("t/t_preproc.v", 394)) begin 
+`line 394 "t/t_preproc.v" 0
+ 
+`line 394 "t/t_preproc.v" 0
+	 message({"Blah-", "clx_scen", " end"}); 
+`line 394 "t/t_preproc.v" 0
+      end 
+`line 394 "t/t_preproc.v" 0
+        
+`line 394 "t/t_preproc.v" 0
+   while(0);
 
-
-
+`line 396 "t/t_preproc.v" 0
+ 
 
 `line 398 "t/t_preproc.v" 0
+ 
+
+
+
+
+`line 402 "t/t_preproc.v" 0
     
-`line 398 "t/t_preproc.v" 0
+`line 402 "t/t_preproc.v" 0
     
 
-`line 399 "t/t_preproc.v" 0
+`line 403 "t/t_preproc.v" 0
      
  
 EXP: This is fooed
@@ -639,7 +644,7 @@ This is fooed
 EXP: This is fooed_2
 This is fooed_2
 
-`line 406 "t/t_preproc.v" 0
+`line 410 "t/t_preproc.v" 0
  
  
 np
@@ -651,11 +656,11 @@ np
  
     
 
-`line 417 "t/t_preproc.v" 0
+`line 421 "t/t_preproc.v" 0
  
     
 
-`line 420 "t/t_preproc.v" 0
+`line 424 "t/t_preproc.v" 0
  
  
  
@@ -664,12 +669,12 @@ np
  
  
 
-`line 428 "t/t_preproc.v" 0
- 
- 
- 
-
 `line 432 "t/t_preproc.v" 0
+ 
+ 
+ 
+
+`line 436 "t/t_preproc.v" 0
 hello3hello3hello3
 hello4hello4hello4hello4
  
@@ -677,7 +682,7 @@ hello4hello4hello4hello4
  
  
  
-`line 438 "t/t_preproc.v" 0
+`line 442 "t/t_preproc.v" 0
 `line 1 "t/t_preproc_inc4.vh" 1
  
 `line 2 "t/t_preproc_inc4.vh" 0
@@ -689,9 +694,9 @@ hello4hello4hello4hello4
  
 
 `line 8 "t/t_preproc_inc4.vh" 2
-`line 438 "t/t_preproc.v" 0
+`line 442 "t/t_preproc.v" 0
 
-`line 439 "t/t_preproc.v" 0
+`line 443 "t/t_preproc.v" 0
    
  
  
@@ -701,28 +706,28 @@ hello4hello4hello4hello4
  
  
      
-`line 447 "t/t_preproc.v" 0
+`line 451 "t/t_preproc.v" 0
  
      
      
      
-Line_Preproc_Check 451
+Line_Preproc_Check 455
  
  
  
 
  
-Line_Preproc_Check 457
+Line_Preproc_Check 461
 "FOO \
   BAR " "arg_line1 \
   arg_line2" "FOO \
   BAR "
-`line 460 "t/t_preproc.v" 0
-Line_Preproc_Check 460
+`line 464 "t/t_preproc.v" 0
+Line_Preproc_Check 464
  
  
 
-`line 464 "t/t_preproc.v" 0
+`line 468 "t/t_preproc.v" 0
  
  
  
@@ -733,14 +738,14 @@ abc
  
  
 
-`line 474 "t/t_preproc.v" 0
+`line 478 "t/t_preproc.v" 0
  
  
  
 EXP: sonet_frame
 sonet_frame
 
-`line 480 "t/t_preproc.v" 0
+`line 484 "t/t_preproc.v" 0
  
  
 EXP: sonet_frame
@@ -751,7 +756,7 @@ sonet_frame
 EXP: sonet_frame
 sonet_frame
 
-`line 490 "t/t_preproc.v" 0
+`line 494 "t/t_preproc.v" 0
  
  
  
@@ -759,13 +764,13 @@ EXP: module zzz ; endmodule
 module zzz ; endmodule
 module zzz ; endmodule
 
-`line 497 "t/t_preproc.v" 0
+`line 501 "t/t_preproc.v" 0
  
 EXP: module a_b ; endmodule
 module a_b ; endmodule
 module a_b ; endmodule
 
-`line 502 "t/t_preproc.v" 0
+`line 506 "t/t_preproc.v" 0
  
  
 integer foo;
@@ -779,7 +784,7 @@ module t;
  
 
    initial begin : \`LEX_CAT(a[0],_assignment)  
-`line 514 "t/t_preproc.v" 0
+`line 518 "t/t_preproc.v" 0
    $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) ");   end
     
     
@@ -788,7 +793,7 @@ module t;
  
 
    initial begin : \a[0]_assignment_a[1] 
-`line 521 "t/t_preproc.v" 0
+`line 525 "t/t_preproc.v" 0
    $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] ");   end
  
     
@@ -804,7 +809,7 @@ module t;
 
     
    initial begin : \`CAT(ff,bb) 
-`line 535 "t/t_preproc.v" 0
+`line 539 "t/t_preproc.v" 0
    $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) ");   end
    
     
@@ -812,7 +817,7 @@ module t;
 
     
    initial begin : \`zzz 
-`line 541 "t/t_preproc.v" 0
+`line 545 "t/t_preproc.v" 0
    $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz ");   end
  
     
@@ -821,11 +826,11 @@ module t;
 
     
    initial begin : \`FOO 
-`line 548 "t/t_preproc.v" 0
+`line 552 "t/t_preproc.v" 0
     $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO ");  end
     
    initial begin : \xx`FOO 
-`line 550 "t/t_preproc.v" 0
+`line 554 "t/t_preproc.v" 0
    $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO ");  end
    
     
@@ -858,27 +863,27 @@ module t;
  
 
    initial 
-`line 581 "t/t_preproc.v" 0
+`line 585 "t/t_preproc.v" 0
        $display("%s%s","a1","b2c3\n");
 endmodule
 
-`line 584 "t/t_preproc.v" 0
+`line 588 "t/t_preproc.v" 0
  
  
 
-`line 587 "t/t_preproc.v" 0
+`line 591 "t/t_preproc.v" 0
  
  
 $display("RAM0");
 $display("CPU");
 
-`line 592 "t/t_preproc.v" 0
+`line 596 "t/t_preproc.v" 0
  
  
  
  
 
-`line 597 "t/t_preproc.v" 0
+`line 601 "t/t_preproc.v" 0
  
 XXE_FAMILY = XXE_
  
@@ -886,7 +891,7 @@ XXE_FAMILY = XXE_
      $display("XXE_ is defined");
 
 
-`line 604 "t/t_preproc.v" 0
+`line 608 "t/t_preproc.v" 0
  
 XYE_FAMILY = XYE_
  
@@ -894,7 +899,7 @@ XYE_FAMILY = XYE_
      $display("XYE_ is defined");
 
 
-`line 611 "t/t_preproc.v" 0
+`line 615 "t/t_preproc.v" 0
  
 XXS_FAMILY = XXS_some
  
@@ -902,7 +907,7 @@ XXS_FAMILY = XXS_some
      $display("XXS_some is defined");
 
 
-`line 618 "t/t_preproc.v" 0
+`line 622 "t/t_preproc.v" 0
  
 XYS_FAMILY = XYS_foo
  
@@ -910,10 +915,10 @@ XYS_FAMILY = XYS_foo
      $display("XYS_foo is defined");
 
 
-`line 625 "t/t_preproc.v" 0
+`line 629 "t/t_preproc.v" 0
  
 
-`line 627 "t/t_preproc.v" 0
+`line 631 "t/t_preproc.v" 0
  
   
   
@@ -922,7 +927,7 @@ XYS_FAMILY = XYS_foo
      
  
 
-`line 635 "t/t_preproc.v" 0
+`line 639 "t/t_preproc.v" 0
   
   
   
@@ -930,7 +935,7 @@ XYS_FAMILY = XYS_foo
      
  
 
-`line 642 "t/t_preproc.v" 0
+`line 646 "t/t_preproc.v" 0
   
   
   
@@ -938,7 +943,7 @@ XYS_FAMILY = XYS_foo
      
  
 
-`line 649 "t/t_preproc.v" 0
+`line 653 "t/t_preproc.v" 0
   
   
   
@@ -946,26 +951,26 @@ XYS_FAMILY = XYS_foo
      
  
 
-`line 656 "t/t_preproc.v" 0
-  
-
-`line 658 "t/t_preproc.v" 0
-  
-
 `line 660 "t/t_preproc.v" 0
- 
- 
-(.mySig (myInterface.pa5),
+  
+
+`line 662 "t/t_preproc.v" 0
+  
 
 `line 664 "t/t_preproc.v" 0
  
  
+(.mySig (myInterface.pa5),
 
-`line 667 "t/t_preproc.v" 0
+`line 668 "t/t_preproc.v" 0
+ 
+ 
+
+`line 671 "t/t_preproc.v" 0
  
 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp"));
 
-`line 670 "t/t_preproc.v" 0
+`line 674 "t/t_preproc.v" 0
  
  
 
@@ -974,28 +979,28 @@ XYS_FAMILY = XYS_foo
 
 
 
-`line 678 "t/t_preproc.v" 0
+`line 682 "t/t_preproc.v" 0
 module pcc2_cfg;
   generate
    
-`line 680 "t/t_preproc.v" 0
+`line 684 "t/t_preproc.v" 0
   covergroup a @(posedge b); 
-`line 680 "t/t_preproc.v" 0
+`line 684 "t/t_preproc.v" 0
     c: coverpoint d iff ((c) === 1'b1); endgroup 
-`line 680 "t/t_preproc.v" 0
+`line 684 "t/t_preproc.v" 0
       a u_a; 
-`line 680 "t/t_preproc.v" 0
+`line 684 "t/t_preproc.v" 0
    initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0);
   endgenerate
 endmodule
 
-`line 684 "t/t_preproc.v" 0
+`line 688 "t/t_preproc.v" 0
  
  
  
 "`NOT_DEFINED_STR"
 
-`line 689 "t/t_preproc.v" 0
+`line 693 "t/t_preproc.v" 0
  
  
    
@@ -1018,4 +1023,4 @@ predef 2 2
  
  
 
-`line 711 "t/t_preproc.v" 2
+`line 715 "t/t_preproc.v" 2
diff --git a/test_regress/t/t_preproc.v b/test_regress/t/t_preproc.v
index a52ce02c1..50f18e53d 100644
--- a/test_regress/t/t_preproc.v
+++ b/test_regress/t/t_preproc.v
@@ -208,6 +208,10 @@ ZCBXb3JrIGFzIG==
 
 `pragma protect end_protected
 
+// encoding envelope
+`pragma protect
+`pragma protect end
+
 endmodule
 
 //======================================================================
diff --git a/test_regress/t/t_preproc_comments.out b/test_regress/t/t_preproc_comments.out
index 1d2795895..881de7e8d 100644
--- a/test_regress/t/t_preproc_comments.out
+++ b/test_regress/t/t_preproc_comments.out
@@ -325,9 +325,14 @@ ZCBXb3JrIGFzIG==
 `pragma protect end_protected
 
 `line 211 "t/t_preproc.v" 0
+// encoding envelope 
+`pragma protect
+`pragma protect end
+
+`line 215 "t/t_preproc.v" 0
 endmodule
 
-`line 213 "t/t_preproc.v" 0
+`line 217 "t/t_preproc.v" 0
 //====================================================================== 
 // macro call with define that has comma 
  
@@ -338,17 +343,17 @@ endmodule
  
  
 
-`line 223 "t/t_preproc.v" 0
+`line 227 "t/t_preproc.v" 0
 begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
 begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
 begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end  more
 
-`line 227 "t/t_preproc.v" 0
+`line 231 "t/t_preproc.v" 0
 //====================================================================== 
 // include of parameterized file 
  
  
-`line 230 "t/t_preproc.v" 0
+`line 234 "t/t_preproc.v" 0
 `line 1 "t/t_preproc_inc4.vh" 1
 // DESCRIPTION: Verilog::Preproc: Example source code 
 `line 2 "t/t_preproc_inc4.vh" 0
@@ -360,57 +365,57 @@ begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end  more
  
 
 `line 8 "t/t_preproc_inc4.vh" 2
-`line 230 "t/t_preproc.v" 0
-
-`line 231 "t/t_preproc.v" 0
- 
-  
-
 `line 234 "t/t_preproc.v" 0
- 
 
-`line 236 "t/t_preproc.v" 0
+`line 235 "t/t_preproc.v" 0
  
   
 
+`line 238 "t/t_preproc.v" 0
+ 
 
 `line 240 "t/t_preproc.v" 0
+ 
+  
+
+
+`line 244 "t/t_preproc.v" 0
 //====================================================================== 
 // macro call with , in {} 
 
-`line 243 "t/t_preproc.v" 0
+`line 247 "t/t_preproc.v" 0
  
 $blah("ab,cd","e,f");
 $blah(this.logfile,vec);
 $blah(this.logfile,vec[1,2,3]);
 $blah(this.logfile,{blah.name(), " is not foo"});
 
-`line 249 "t/t_preproc.v" 0
+`line 253 "t/t_preproc.v" 0
 //====================================================================== 
 // pragma/default net type 
 
-`line 252 "t/t_preproc.v" 0
+`line 256 "t/t_preproc.v" 0
 `pragma foo = 1
 `default_nettype none
 `default_nettype uwire
 
-`line 256 "t/t_preproc.v" 0
+`line 260 "t/t_preproc.v" 0
 //====================================================================== 
 // Ifdef 
 
-`line 259 "t/t_preproc.v" 0
+`line 263 "t/t_preproc.v" 0
  
  
    
 
-`line 263 "t/t_preproc.v" 0
-Line_Preproc_Check 263
+`line 267 "t/t_preproc.v" 0
+Line_Preproc_Check 267
 
-`line 265 "t/t_preproc.v" 0
+`line 269 "t/t_preproc.v" 0
 //====================================================================== 
 // bug84 
 
-`line 268 "t/t_preproc.v" 0
+`line 272 "t/t_preproc.v" 0
  // Hello, comments MIGHT not be legal /*more,,)cmts*/ // But newlines ARE legal... who speced THAT? 
 
 
@@ -418,15 +423,15 @@ Line_Preproc_Check 263
 
 
 
-`line 275 "t/t_preproc.v" 0
+`line 279 "t/t_preproc.v" 0
 (//Here 	      x,y   //Too) 
-Line_Preproc_Check 276
+Line_Preproc_Check 280
 
-`line 278 "t/t_preproc.v" 0
+`line 282 "t/t_preproc.v" 0
 //====================================================================== 
 // defines split arguments 
 
-`line 281 "t/t_preproc.v" 0
+`line 285 "t/t_preproc.v" 0
  
  
  
@@ -435,17 +440,17 @@ beginend   // 2001 spec doesn't require two tokens, so "beginend" ok
 beginend    // 2001 spec doesn't require two tokens, so "beginend" ok 
 "beginend"  // No space "beginend" 
 
-`line 289 "t/t_preproc.v" 0
+`line 293 "t/t_preproc.v" 0
 //====================================================================== 
 // bug106 
  
  
   `\esc`def
 
-`line 295 "t/t_preproc.v" 0
+`line 299 "t/t_preproc.v" 0
 Not a \`define
 
-`line 297 "t/t_preproc.v" 0
+`line 301 "t/t_preproc.v" 0
 //====================================================================== 
 // misparsed comma in submacro 
  
@@ -454,23 +459,23 @@ Not a \`define
  
 x,y)--bee  submacro has comma paren
 
-`line 305 "t/t_preproc.v" 0
+`line 309 "t/t_preproc.v" 0
 //====================================================================== 
 // bug191 
  
 $display("10 %d %d", $bits(foo), 10);
 
-`line 310 "t/t_preproc.v" 0
+`line 314 "t/t_preproc.v" 0
 //====================================================================== 
 // 1800-2009 
  
     
 
-`line 315 "t/t_preproc.v" 0
+`line 319 "t/t_preproc.v" 0
     
     
 
-`line 318 "t/t_preproc.v" 0
+`line 322 "t/t_preproc.v" 0
 //====================================================================== 
 // bug202 
  
@@ -485,34 +490,34 @@ $display("10 %d %d", $bits(foo), 10);
 
 
 
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
 
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
    							
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
          	
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
       
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
 					
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
   								
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
      					
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
           		
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
     							
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
      assign a3 = ~b3 ;						
-`line 332 "t/t_preproc.v" 0
+`line 336 "t/t_preproc.v" 0
   
 
-`line 334 "t/t_preproc.v" 0
+`line 338 "t/t_preproc.v" 0
  
 /* multi	\
 	 line1*/ 	\
-`line 336 "t/t_preproc.v" 0
+`line 340 "t/t_preproc.v" 0
  
 /*multi	\
 	   line2*/ 
@@ -521,59 +526,59 @@ $display("10 %d %d", $bits(foo), 10);
 
 
 
-`line 343 "t/t_preproc.v" 0
+`line 347 "t/t_preproc.v" 0
 
-`line 343 "t/t_preproc.v" 0
+`line 347 "t/t_preproc.v" 0
    
-`line 343 "t/t_preproc.v" 0
+`line 347 "t/t_preproc.v" 0
 /* multi		
       line 3*/ 		
-`line 343 "t/t_preproc.v" 0
+`line 347 "t/t_preproc.v" 0
    def i		
 
 
-`line 345 "t/t_preproc.v" 0
+`line 349 "t/t_preproc.v" 0
 //====================================================================== 
 
-`line 347 "t/t_preproc.v" 0
- 
- 
- 
-
-
 `line 351 "t/t_preproc.v" 0
  
+ 
+ 
+
+
+`line 355 "t/t_preproc.v" 0
+ 
 
  
 
 
 
-`line 357 "t/t_preproc.v" 0
+`line 361 "t/t_preproc.v" 0
 1 // verilator NOT IN DEFINE (nodef) 
 2 /* verilator PART OF DEFINE */  (hasdef)
 3 
-`line 359 "t/t_preproc.v" 0
+`line 363 "t/t_preproc.v" 0
 /* verilator NOT PART
 	        OF DEFINE */  (nodef)
-`line 360 "t/t_preproc.v" 0
+`line 364 "t/t_preproc.v" 0
 4 
-`line 360 "t/t_preproc.v" 0
+`line 364 "t/t_preproc.v" 0
 /* verilator PART 
 	        OF DEFINE */  (nodef)
-`line 361 "t/t_preproc.v" 0
+`line 365 "t/t_preproc.v" 0
 5 also in  
-`line 361 "t/t_preproc.v" 0
+`line 365 "t/t_preproc.v" 0
   also3  // CMT NOT (nodef) 
  
 
 HAS a NEW 
-`line 364 "t/t_preproc.v" 0
+`line 368 "t/t_preproc.v" 0
 LINE
 
-`line 366 "t/t_preproc.v" 0
+`line 370 "t/t_preproc.v" 0
 //====================================================================== 
 
-`line 368 "t/t_preproc.v" 0
+`line 372 "t/t_preproc.v" 0
  
 
 
@@ -587,11 +592,11 @@ LINE
 
 
 
-`line 381 "t/t_preproc.v" 0
+`line 385 "t/t_preproc.v" 0
  
  
 
-`line 384 "t/t_preproc.v" 0
+`line 388 "t/t_preproc.v" 0
 EXP: clxx_scen
 clxx_scen
 EXP: clxx_scen
@@ -599,44 +604,44 @@ EXP: clxx_scen
  
 EXP: do if (start("verilog/inc1.v", 25)) begin  message({"Blah-", "clx_scen", " end"}); end  while(0);
 
-`line 390 "t/t_preproc.v" 0
+`line 394 "t/t_preproc.v" 0
    do 
-`line 390 "t/t_preproc.v" 0
+`line 394 "t/t_preproc.v" 0
       /* synopsys translate_off */  
-`line 390 "t/t_preproc.v" 0
+`line 394 "t/t_preproc.v" 0
   
-`line 390 "t/t_preproc.v" 0
+`line 394 "t/t_preproc.v" 0
     
-`line 390 "t/t_preproc.v" 0
- 
-`line 390 "t/t_preproc.v" 0
-      if (start("t/t_preproc.v", 390)) begin 
-`line 390 "t/t_preproc.v" 0
- 
-`line 390 "t/t_preproc.v" 0
-	 message({"Blah-", "clx_scen", " end"}); 
-`line 390 "t/t_preproc.v" 0
-      end 
-`line 390 "t/t_preproc.v" 0
-      /* synopsys translate_on */  
-`line 390 "t/t_preproc.v" 0
-   while(0);
-
-`line 392 "t/t_preproc.v" 0
-//====================================================================== 
-
 `line 394 "t/t_preproc.v" 0
  
+`line 394 "t/t_preproc.v" 0
+      if (start("t/t_preproc.v", 394)) begin 
+`line 394 "t/t_preproc.v" 0
+ 
+`line 394 "t/t_preproc.v" 0
+	 message({"Blah-", "clx_scen", " end"}); 
+`line 394 "t/t_preproc.v" 0
+      end 
+`line 394 "t/t_preproc.v" 0
+      /* synopsys translate_on */  
+`line 394 "t/t_preproc.v" 0
+   while(0);
 
-
-
+`line 396 "t/t_preproc.v" 0
+//====================================================================== 
 
 `line 398 "t/t_preproc.v" 0
+ 
+
+
+
+
+`line 402 "t/t_preproc.v" 0
     
-`line 398 "t/t_preproc.v" 0
+`line 402 "t/t_preproc.v" 0
     
 
-`line 399 "t/t_preproc.v" 0
+`line 403 "t/t_preproc.v" 0
      
 //`ifndef def_fooed_2  `error "No def_fooed_2" `endif 
 EXP: This is fooed
@@ -644,7 +649,7 @@ This is fooed
 EXP: This is fooed_2
 This is fooed_2
 
-`line 406 "t/t_preproc.v" 0
+`line 410 "t/t_preproc.v" 0
 //====================================================================== 
  
 np
@@ -656,11 +661,11 @@ np
  
     
 
-`line 417 "t/t_preproc.v" 0
+`line 421 "t/t_preproc.v" 0
  
     
 
-`line 420 "t/t_preproc.v" 0
+`line 424 "t/t_preproc.v" 0
 //====================================================================== 
 // Metaprogramming 
  
@@ -669,12 +674,12 @@ np
  
  
 
-`line 428 "t/t_preproc.v" 0
+`line 432 "t/t_preproc.v" 0
  
  
  
 
-`line 432 "t/t_preproc.v" 0
+`line 436 "t/t_preproc.v" 0
 hello3hello3hello3
 hello4hello4hello4hello4
 //====================================================================== 
@@ -682,7 +687,7 @@ hello4hello4hello4hello4
  
  
  
-`line 438 "t/t_preproc.v" 0
+`line 442 "t/t_preproc.v" 0
 `line 1 "t/t_preproc_inc4.vh" 1
 // DESCRIPTION: Verilog::Preproc: Example source code 
 `line 2 "t/t_preproc_inc4.vh" 0
@@ -694,9 +699,9 @@ hello4hello4hello4hello4
  
 
 `line 8 "t/t_preproc_inc4.vh" 2
-`line 438 "t/t_preproc.v" 0
+`line 442 "t/t_preproc.v" 0
 
-`line 439 "t/t_preproc.v" 0
+`line 443 "t/t_preproc.v" 0
    
 //====================================================================== 
 // Defines doing defines 
@@ -706,28 +711,28 @@ hello4hello4hello4hello4
  
  
      
-`line 447 "t/t_preproc.v" 0
+`line 451 "t/t_preproc.v" 0
  
      
      
      
-Line_Preproc_Check 451
+Line_Preproc_Check 455
 //====================================================================== 
 // Quoted multiline - track line numbers, and ensure \\n gets propagated 
  
 
  
-Line_Preproc_Check 457
+Line_Preproc_Check 461
 "FOO \
   BAR " "arg_line1 \
   arg_line2" "FOO \
   BAR "
-`line 460 "t/t_preproc.v" 0
-Line_Preproc_Check 460
+`line 464 "t/t_preproc.v" 0
+Line_Preproc_Check 464
 //====================================================================== 
 // bug283 
 
-`line 464 "t/t_preproc.v" 0
+`line 468 "t/t_preproc.v" 0
  
  
  
@@ -738,14 +743,14 @@ abc
  
  
 
-`line 474 "t/t_preproc.v" 0
+`line 478 "t/t_preproc.v" 0
  
  
  
 EXP: sonet_frame
 sonet_frame
 
-`line 480 "t/t_preproc.v" 0
+`line 484 "t/t_preproc.v" 0
  
  
 EXP: sonet_frame
@@ -756,7 +761,7 @@ sonet_frame
 EXP: sonet_frame
 sonet_frame
 
-`line 490 "t/t_preproc.v" 0
+`line 494 "t/t_preproc.v" 0
 // The existance of non-existance of a base define can make a difference 
  
  
@@ -764,13 +769,13 @@ EXP: module zzz ; endmodule
 module zzz ; endmodule
 module zzz ; endmodule
 
-`line 497 "t/t_preproc.v" 0
+`line 501 "t/t_preproc.v" 0
  
 EXP: module a_b ; endmodule
 module a_b ; endmodule
 module a_b ; endmodule
 
-`line 502 "t/t_preproc.v" 0
+`line 506 "t/t_preproc.v" 0
 //====================================================================== 
 // bug311 
 integer/*NEED_SPACE*/ foo;
@@ -784,7 +789,7 @@ module t;
  
 
    initial begin : \`LEX_CAT(a[0],_assignment)  
-`line 514 "t/t_preproc.v" 0
+`line 518 "t/t_preproc.v" 0
    $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) ");   end
    //----- 
    // SHOULD(simulator-dependant): Backslash doesn't prevent arguments from 
@@ -793,7 +798,7 @@ module t;
  
 
    initial begin : \a[0]_assignment_a[1] 
-`line 521 "t/t_preproc.v" 0
+`line 525 "t/t_preproc.v" 0
    $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] ");   end
  
    //----- 
@@ -809,7 +814,7 @@ module t;
 
    // Similar to above; \ does not allow expansion after substitution 
    initial begin : \`CAT(ff,bb) 
-`line 535 "t/t_preproc.v" 0
+`line 539 "t/t_preproc.v" 0
    $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) ");   end
    
    //----- 
@@ -817,7 +822,7 @@ module t;
 
    // MUST: Unknown macro with backslash escape stays as escaped symbol name 
    initial begin : \`zzz 
-`line 541 "t/t_preproc.v" 0
+`line 545 "t/t_preproc.v" 0
    $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz ");   end
  
    //----- 
@@ -826,11 +831,11 @@ module t;
 
    // SHOULD(simulator-dependant): Known macro with backslash escape expands 
    initial begin : \`FOO 
-`line 548 "t/t_preproc.v" 0
+`line 552 "t/t_preproc.v" 0
     $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO ");  end
    // SHOULD(simulator-dependant): Prefix breaks the above 
    initial begin : \xx`FOO 
-`line 550 "t/t_preproc.v" 0
+`line 554 "t/t_preproc.v" 0
    $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO ");  end
    
    //----- 
@@ -863,27 +868,27 @@ module t;
  
 
    initial 
-`line 581 "t/t_preproc.v" 0
+`line 585 "t/t_preproc.v" 0
        $display("%s%s","a1","b2c3\n");
 endmodule
 
-`line 584 "t/t_preproc.v" 0
+`line 588 "t/t_preproc.v" 0
 //====================================================================== 
 //bug1225 
 
-`line 587 "t/t_preproc.v" 0
+`line 591 "t/t_preproc.v" 0
  
  
 $display("RAM0");
 $display("CPU");
 
-`line 592 "t/t_preproc.v" 0
+`line 596 "t/t_preproc.v" 0
  
  
  
  
 
-`line 597 "t/t_preproc.v" 0
+`line 601 "t/t_preproc.v" 0
  
 XXE_FAMILY = XXE_
  
@@ -891,7 +896,7 @@ XXE_FAMILY = XXE_
      $display("XXE_ is defined");
 
 
-`line 604 "t/t_preproc.v" 0
+`line 608 "t/t_preproc.v" 0
  
 XYE_FAMILY = XYE_
  
@@ -899,7 +904,7 @@ XYE_FAMILY = XYE_
      $display("XYE_ is defined");
 
 
-`line 611 "t/t_preproc.v" 0
+`line 615 "t/t_preproc.v" 0
  
 XXS_FAMILY = XXS_some
  
@@ -907,7 +912,7 @@ XXS_FAMILY = XXS_some
      $display("XXS_some is defined");
 
 
-`line 618 "t/t_preproc.v" 0
+`line 622 "t/t_preproc.v" 0
  
 XYS_FAMILY = XYS_foo
  
@@ -915,10 +920,10 @@ XYS_FAMILY = XYS_foo
      $display("XYS_foo is defined");
 
 
-`line 625 "t/t_preproc.v" 0
+`line 629 "t/t_preproc.v" 0
 //==== 
 
-`line 627 "t/t_preproc.v" 0
+`line 631 "t/t_preproc.v" 0
  
   
   
@@ -927,7 +932,7 @@ XYS_FAMILY = XYS_foo
      
  
 
-`line 635 "t/t_preproc.v" 0
+`line 639 "t/t_preproc.v" 0
   
   
   
@@ -935,7 +940,7 @@ XYS_FAMILY = XYS_foo
      
  
 
-`line 642 "t/t_preproc.v" 0
+`line 646 "t/t_preproc.v" 0
   
   
   
@@ -943,7 +948,7 @@ XYS_FAMILY = XYS_foo
      
  
 
-`line 649 "t/t_preproc.v" 0
+`line 653 "t/t_preproc.v" 0
   
   
   
@@ -951,26 +956,26 @@ XYS_FAMILY = XYS_foo
      
  
 
-`line 656 "t/t_preproc.v" 0
-  
-
-`line 658 "t/t_preproc.v" 0
- // NEVER 
-
 `line 660 "t/t_preproc.v" 0
+  
+
+`line 662 "t/t_preproc.v" 0
+ // NEVER 
+
+`line 664 "t/t_preproc.v" 0
 //bug1227 
  
 (.mySig (myInterface.pa5),
 
-`line 664 "t/t_preproc.v" 0
+`line 668 "t/t_preproc.v" 0
 //====================================================================== 
 // Stringify bug 
 
-`line 667 "t/t_preproc.v" 0
+`line 671 "t/t_preproc.v" 0
  
 `dbg_hdl(UVM_LOW, ("Functional coverage enabled: paramgrp"));
 
-`line 670 "t/t_preproc.v" 0
+`line 674 "t/t_preproc.v" 0
  
  
 
@@ -979,28 +984,28 @@ XYS_FAMILY = XYS_foo
 
 
 
-`line 678 "t/t_preproc.v" 0
+`line 682 "t/t_preproc.v" 0
 module pcc2_cfg;
   generate
    
-`line 680 "t/t_preproc.v" 0
+`line 684 "t/t_preproc.v" 0
   covergroup a @(posedge b); 
-`line 680 "t/t_preproc.v" 0
+`line 684 "t/t_preproc.v" 0
     c: coverpoint d iff ((c) === 1'b1); endgroup 
-`line 680 "t/t_preproc.v" 0
+`line 684 "t/t_preproc.v" 0
       a u_a; 
-`line 680 "t/t_preproc.v" 0
+`line 684 "t/t_preproc.v" 0
    initial do begin $display ("DEBUG : %s [%m]", $sformatf ("Functional coverage enabled: u_a")); end while(0);
   endgenerate
 endmodule
 
-`line 684 "t/t_preproc.v" 0
+`line 688 "t/t_preproc.v" 0
 //====================================================================== 
 // Verilog-Perl bug1668 
  
 "`NOT_DEFINED_STR"
 
-`line 689 "t/t_preproc.v" 0
+`line 693 "t/t_preproc.v" 0
 //====================================================================== 
 // IEEE mandated predefines 
   // undefineall should have no effect on these 
@@ -1023,4 +1028,4 @@ predef 2 2
 // After `undefineall above, for testing --dump-defines 
  
 
-`line 711 "t/t_preproc.v" 2
+`line 715 "t/t_preproc.v" 2