Merge from master

This commit is contained in:
Wilson Snyder 2018-07-22 11:53:58 -04:00
commit 0ef3baa87d
3 changed files with 8 additions and 14 deletions

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@ -630,12 +630,8 @@ WARN_LOGFILE =
# with spaces.
INPUT = doxygen-mainpage \
include \
include \
src \
test_c \
test_regress \
test_sc \
test_v
# This tag can be used to specify the character encoding of the source files
# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is

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@ -327,7 +327,7 @@ public: // But internals only - called from VerilatedModule's
class Verilated {
// MEMBERS
// Slow path variables
static VerilatedMutex m_mutex; ///< Mutex for all static members, when VL_THREADED
static VerilatedMutex m_mutex; ///< Mutex for s_s/s_ns members, when VL_THREADED
static VerilatedVoidCb s_flushCb; ///< Flush callback function

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@ -358,21 +358,19 @@ typedef unsigned long long vluint64_t; ///< 64-bit unsigned type
//=========================================================================
// Performance counters
#if VL_THREADED
/// The vluint64_t argument is loaded with a high-performance counter for profiling
/// or 0x0 if not implemeted on this platform
# if defined(__i386__) || defined(__x86_64__)
# define VL_RDTSC(val) { \
#if defined(__i386__) || defined(__x86_64__)
# define VL_RDTSC(val) { \
vluint32_t hi, lo; \
asm volatile("rdtsc" : "=a" (lo), "=d" (hi)); \
(val) = ((vluint64_t)lo) | (((vluint64_t)hi)<<32); \
}
# elif defined(__aarch64__)
# define VL_RDTSC(val) asm volatile("mrs %[rt],PMCCNTR_EL0" : [rt] "=r" (val));
# else
#elif defined(__aarch64__)
# define VL_RDTSC(val) asm volatile("mrs %[rt],PMCCNTR_EL0" : [rt] "=r" (val));
#else
// We just silently ignore unknown OSes, as only leads to missing statistics
# define VL_RDTSC(val) (val) = 0;
# endif
# define VL_RDTSC(val) (val) = 0;
#endif
//=========================================================================