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Add PINNOTFOUND warning in place of "Pin not found" error (#2868)
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@ -4740,6 +4740,34 @@ Warns that an instance has a pin which is not connected to another signal.
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Disabled by default as this is a code style warning; it will simulate
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correctly.
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=item PINNOTFOUND
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Warns that an instance port or Parameter was not found in the module being
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instanciated. Please note that Verilator raises these errors also on instances
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that should be disabled by generate/if/endgenerate constructs:
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module a;
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localparam A=1;
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generate
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if (A==0) begin
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b b_inst1 (.x(1'b0)); // nonexistent port
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b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter
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end
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endgenerate
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endmodule
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module b;
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endmodule
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In the example above, b is instantiated with a port named x, but module b has
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no such port. In the next line, b is instantiated again with
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a nonexistent parameter PX. Technically, this code is incorrect because of
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this, but other tools may ignore it because module b is not instantiated
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due to the generate/if condition being false.
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It is possible to disable the error above using:
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/* verilator lint_off PINNOTFOUND */
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=item PKGNODECL
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Error that a package/class appears to have been referenced that has not yet
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@ -82,6 +82,7 @@ Tobias Wölfel
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Todd Strader
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Tomasz Gorochowik
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Tymoteusz Blazejczyk
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Udi Finkelstein
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Unai Martinez-Corral
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Vassilis Papaefstathiou
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Veripool API Bot
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@ -101,9 +101,10 @@ public:
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MULTIDRIVEN, // Driven from multiple blocks
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MULTITOP, // Multiple top level modules
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NOLATCH, // No latch detected in always_latch block
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PINCONNECTEMPTY,// Cell pin connected by name with empty reference
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PINMISSING, // Cell pin not specified
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PINNOCONNECT, // Cell pin not connected
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PINCONNECTEMPTY,// Cell pin connected by name with empty reference
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PINNOTFOUND, // instance port name not found in it's module
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PKGNODECL, // Error: Package/class needs to be predeclared
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PROCASSWIRE, // Procedural assignment on wire
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RANDC, // Unsupported: 'randc' converted to 'rand'
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@ -166,8 +167,8 @@ public:
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"IMPERFECTSCH", "IMPLICIT", "IMPORTSTAR", "IMPURE",
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"INCABSPATH", "INFINITELOOP", "INITIALDLY", "INSECURE",
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"LATCH", "LITENDIAN", "MODDUP",
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"MULTIDRIVEN", "MULTITOP","NOLATCH",
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"PINMISSING", "PINNOCONNECT", "PINCONNECTEMPTY", "PKGNODECL", "PROCASSWIRE",
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"MULTIDRIVEN", "MULTITOP","NOLATCH", "PINCONNECTEMPTY",
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"PINMISSING", "PINNOCONNECT", "PINNOTFOUND", "PKGNODECL", "PROCASSWIRE",
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"RANDC", "REALCVT", "REDEFMACRO",
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"SELRANGE", "SHORTREAL", "SPLITVAR", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET",
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"TICKCOUNT", "TIMESCALEMOD",
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@ -190,7 +191,8 @@ public:
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// Later -Werror- options may make more of these.
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bool pretendError() const {
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return (m_e == ASSIGNIN || m_e == BLKANDNBLK || m_e == BLKLOOPINIT || m_e == CONTASSREG
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|| m_e == IMPURE || m_e == PKGNODECL || m_e == PROCASSWIRE); // Says IEEE
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|| m_e == IMPURE || m_e == PINNOTFOUND || m_e == PKGNODECL
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|| m_e == PROCASSWIRE); // Says IEEE
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}
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// Warnings to mention manual
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bool mentionManual() const {
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@ -2023,9 +2023,10 @@ private:
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LinkNodeMatcherVarParam())
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: m_statep->suggestSymFlat(m_pinSymp, nodep->name(),
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LinkNodeMatcherVarIO()));
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nodep->v3error(ucfirst(whatp)
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<< " not found: " << nodep->prettyNameQ() << '\n'
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<< (suggest.empty() ? "" : nodep->warnMore() + suggest));
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nodep->v3warn(PINNOTFOUND,
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ucfirst(whatp)
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<< " not found: " << nodep->prettyNameQ() << '\n'
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<< (suggest.empty() ? "" : nodep->warnMore() + suggest));
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} else if (AstVar* refp = VN_CAST(foundp->nodep(), Var)) {
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if (!refp->isIO() && !refp->isParam() && !refp->isIfaceRef()) {
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nodep->v3error(ucfirst(whatp) << " is not an in/out/inout/param/interface: "
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@ -1,8 +1,8 @@
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%Error: t/t_class_param_bad.v:12:11: Parameter pin not found: 'PARAMBAD'
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: ... Suggested alternative: 'PARAMB'
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%Error-PINNOTFOUND: t/t_class_param_bad.v:12:11: Parameter pin not found: 'PARAMBAD'
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: ... Suggested alternative: 'PARAMB'
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12 | Cls #(.PARAMBAD(1)) c;
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| ^~~~~~~~
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%Error: t/t_class_param_bad.v:13:14: Parameter pin not found: '__paramNumber2'
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%Error-PINNOTFOUND: t/t_class_param_bad.v:13:14: Parameter pin not found: '__paramNumber2'
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13 | Cls #(13, 1) cd;
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| ^
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%Error: Exiting due to
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@ -8,12 +8,12 @@
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t/t_lint_pindup_bad.v:20:10: ... Location of original pin connection
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20 | .i(i),
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| ^
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%Error: t/t_lint_pindup_bad.v:22:10: Pin not found: 'nexist'
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: ... Suggested alternative: 'exists'
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%Error-PINNOTFOUND: t/t_lint_pindup_bad.v:22:10: Pin not found: 'nexist'
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: ... Suggested alternative: 'exists'
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22 | .nexist(i2)
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| ^~~~~~
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%Error: t/t_lint_pindup_bad.v:16:9: Parameter pin not found: 'NEXIST'
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: ... Suggested alternative: 'EXIST'
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%Error-PINNOTFOUND: t/t_lint_pindup_bad.v:16:9: Parameter pin not found: 'NEXIST'
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: ... Suggested alternative: 'EXIST'
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16 | .NEXIST(1),
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| ^~~~~~
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%Error: t/t_lint_pindup_bad.v:17:9: Duplicate parameter pin connection: 'P'
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13
test_regress/t/t_lint_pinnotfound.pl
Executable file
13
test_regress/t/t_lint_pinnotfound.pl
Executable file
@ -0,0 +1,13 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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lint(
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);
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ok(1);
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1;
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test_regress/t/t_lint_pinnotfound.v
Normal file
20
test_regress/t/t_lint_pinnotfound.v
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@ -0,0 +1,20 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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/* verilator lint_off PINNOTFOUND */
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module a;
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localparam A=1;
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generate
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if (A==0)
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begin
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b b_inst1 (.x(1'b0)); // nonexistent port
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b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter
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end
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endgenerate
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endmodule
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module b;
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endmodule
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7
test_regress/t/t_lint_pinnotfound_bad.out
Normal file
7
test_regress/t/t_lint_pinnotfound_bad.out
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@ -0,0 +1,7 @@
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%Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:12:13: Pin not found: 'x'
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12 | b b_inst1 (.x(1'b0));
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| ^
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%Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:13:6: Parameter pin not found: 'PX'
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13 | b #(.PX(1'b0)) b_inst2 ();
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| ^~
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%Error: Exiting due to
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19
test_regress/t/t_lint_pinnotfound_bad.pl
Executable file
19
test_regress/t/t_lint_pinnotfound_bad.pl
Executable file
@ -0,0 +1,19 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(linter => 1);
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lint(
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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19
test_regress/t/t_lint_pinnotfound_bad.v
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19
test_regress/t/t_lint_pinnotfound_bad.v
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@ -0,0 +1,19 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module a;
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localparam A=1;
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generate
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if (A==0)
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begin
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b b_inst1 (.x(1'b0)); // nonexistent port
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b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter
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end
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endgenerate
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endmodule
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module b;
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endmodule
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