Add PINNOTFOUND warning in place of "Pin not found" error (#2868)

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Udi Finkelstein 2021-04-02 01:17:42 +03:00 committed by GitHub
parent a9f4129b6b
commit 0ea5af40c5
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11 changed files with 124 additions and 14 deletions

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@ -4740,6 +4740,34 @@ Warns that an instance has a pin which is not connected to another signal.
Disabled by default as this is a code style warning; it will simulate
correctly.
=item PINNOTFOUND
Warns that an instance port or Parameter was not found in the module being
instanciated. Please note that Verilator raises these errors also on instances
that should be disabled by generate/if/endgenerate constructs:
module a;
localparam A=1;
generate
if (A==0) begin
b b_inst1 (.x(1'b0)); // nonexistent port
b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter
end
endgenerate
endmodule
module b;
endmodule
In the example above, b is instantiated with a port named x, but module b has
no such port. In the next line, b is instantiated again with
a nonexistent parameter PX. Technically, this code is incorrect because of
this, but other tools may ignore it because module b is not instantiated
due to the generate/if condition being false.
It is possible to disable the error above using:
/* verilator lint_off PINNOTFOUND */
=item PKGNODECL
Error that a package/class appears to have been referenced that has not yet

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@ -82,6 +82,7 @@ Tobias Wölfel
Todd Strader
Tomasz Gorochowik
Tymoteusz Blazejczyk
Udi Finkelstein
Unai Martinez-Corral
Vassilis Papaefstathiou
Veripool API Bot

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@ -101,9 +101,10 @@ public:
MULTIDRIVEN, // Driven from multiple blocks
MULTITOP, // Multiple top level modules
NOLATCH, // No latch detected in always_latch block
PINCONNECTEMPTY,// Cell pin connected by name with empty reference
PINMISSING, // Cell pin not specified
PINNOCONNECT, // Cell pin not connected
PINCONNECTEMPTY,// Cell pin connected by name with empty reference
PINNOTFOUND, // instance port name not found in it's module
PKGNODECL, // Error: Package/class needs to be predeclared
PROCASSWIRE, // Procedural assignment on wire
RANDC, // Unsupported: 'randc' converted to 'rand'
@ -166,8 +167,8 @@ public:
"IMPERFECTSCH", "IMPLICIT", "IMPORTSTAR", "IMPURE",
"INCABSPATH", "INFINITELOOP", "INITIALDLY", "INSECURE",
"LATCH", "LITENDIAN", "MODDUP",
"MULTIDRIVEN", "MULTITOP","NOLATCH",
"PINMISSING", "PINNOCONNECT", "PINCONNECTEMPTY", "PKGNODECL", "PROCASSWIRE",
"MULTIDRIVEN", "MULTITOP","NOLATCH", "PINCONNECTEMPTY",
"PINMISSING", "PINNOCONNECT", "PINNOTFOUND", "PKGNODECL", "PROCASSWIRE",
"RANDC", "REALCVT", "REDEFMACRO",
"SELRANGE", "SHORTREAL", "SPLITVAR", "STMTDLY", "SYMRSVDWORD", "SYNCASYNCNET",
"TICKCOUNT", "TIMESCALEMOD",
@ -190,7 +191,8 @@ public:
// Later -Werror- options may make more of these.
bool pretendError() const {
return (m_e == ASSIGNIN || m_e == BLKANDNBLK || m_e == BLKLOOPINIT || m_e == CONTASSREG
|| m_e == IMPURE || m_e == PKGNODECL || m_e == PROCASSWIRE); // Says IEEE
|| m_e == IMPURE || m_e == PINNOTFOUND || m_e == PKGNODECL
|| m_e == PROCASSWIRE); // Says IEEE
}
// Warnings to mention manual
bool mentionManual() const {

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@ -2023,9 +2023,10 @@ private:
LinkNodeMatcherVarParam())
: m_statep->suggestSymFlat(m_pinSymp, nodep->name(),
LinkNodeMatcherVarIO()));
nodep->v3error(ucfirst(whatp)
<< " not found: " << nodep->prettyNameQ() << '\n'
<< (suggest.empty() ? "" : nodep->warnMore() + suggest));
nodep->v3warn(PINNOTFOUND,
ucfirst(whatp)
<< " not found: " << nodep->prettyNameQ() << '\n'
<< (suggest.empty() ? "" : nodep->warnMore() + suggest));
} else if (AstVar* refp = VN_CAST(foundp->nodep(), Var)) {
if (!refp->isIO() && !refp->isParam() && !refp->isIfaceRef()) {
nodep->v3error(ucfirst(whatp) << " is not an in/out/inout/param/interface: "

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@ -1,8 +1,8 @@
%Error: t/t_class_param_bad.v:12:11: Parameter pin not found: 'PARAMBAD'
: ... Suggested alternative: 'PARAMB'
%Error-PINNOTFOUND: t/t_class_param_bad.v:12:11: Parameter pin not found: 'PARAMBAD'
: ... Suggested alternative: 'PARAMB'
12 | Cls #(.PARAMBAD(1)) c;
| ^~~~~~~~
%Error: t/t_class_param_bad.v:13:14: Parameter pin not found: '__paramNumber2'
%Error-PINNOTFOUND: t/t_class_param_bad.v:13:14: Parameter pin not found: '__paramNumber2'
13 | Cls #(13, 1) cd;
| ^
%Error: Exiting due to

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@ -8,12 +8,12 @@
t/t_lint_pindup_bad.v:20:10: ... Location of original pin connection
20 | .i(i),
| ^
%Error: t/t_lint_pindup_bad.v:22:10: Pin not found: 'nexist'
: ... Suggested alternative: 'exists'
%Error-PINNOTFOUND: t/t_lint_pindup_bad.v:22:10: Pin not found: 'nexist'
: ... Suggested alternative: 'exists'
22 | .nexist(i2)
| ^~~~~~
%Error: t/t_lint_pindup_bad.v:16:9: Parameter pin not found: 'NEXIST'
: ... Suggested alternative: 'EXIST'
%Error-PINNOTFOUND: t/t_lint_pindup_bad.v:16:9: Parameter pin not found: 'NEXIST'
: ... Suggested alternative: 'EXIST'
16 | .NEXIST(1),
| ^~~~~~
%Error: t/t_lint_pindup_bad.v:17:9: Duplicate parameter pin connection: 'P'

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@ -0,0 +1,13 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
lint(
);
ok(1);
1;

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@ -0,0 +1,20 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
/* verilator lint_off PINNOTFOUND */
module a;
localparam A=1;
generate
if (A==0)
begin
b b_inst1 (.x(1'b0)); // nonexistent port
b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter
end
endgenerate
endmodule
module b;
endmodule

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@ -0,0 +1,7 @@
%Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:12:13: Pin not found: 'x'
12 | b b_inst1 (.x(1'b0));
| ^
%Error-PINNOTFOUND: t/t_lint_pinnotfound_bad.v:13:6: Parameter pin not found: 'PX'
13 | b #(.PX(1'b0)) b_inst2 ();
| ^~
%Error: Exiting due to

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@ -0,0 +1,19 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(linter => 1);
lint(
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

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@ -0,0 +1,19 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module a;
localparam A=1;
generate
if (A==0)
begin
b b_inst1 (.x(1'b0)); // nonexistent port
b #(.PX(1'b0)) b_inst2 (); // nonexistent parameter
end
endgenerate
endmodule
module b;
endmodule