diff --git a/Changes b/Changes index 7605b6256..0330a600e 100644 --- a/Changes +++ b/Changes @@ -16,6 +16,7 @@ indicates the contributor was also the author of the fix; Thanks! **** Fix false command not found warning in makefiles. [Ruben Diez] +**** Fix hang when functions inside begin block. [David Welch] * Verilator 3.831 2012/01/20 diff --git a/src/V3Begin.cpp b/src/V3Begin.cpp index fb4fe8920..752d94886 100644 --- a/src/V3Begin.cpp +++ b/src/V3Begin.cpp @@ -70,9 +70,20 @@ private: m_modp = NULL; } virtual void visit(AstNodeFTask* nodep, AstNUser*) { - m_ftaskp = nodep; - nodep->iterateChildren(*this); - m_ftaskp = NULL; + UINFO(8," "<iterateChildren(*this); + m_ftaskp = NULL; + } + m_namedScope = oldScope; + m_unnamedScope = oldUnnamed; } virtual void visit(AstBegin* nodep, AstNUser*) { // Begin blocks were only useful in variable creation, change names and delete @@ -80,7 +91,7 @@ private: string oldScope = m_namedScope; string oldUnnamed = m_unnamedScope; { - //UINFO(8,"nname "<name() != "") { // Else unneeded unnamed block // Create data for dotted variable resolution string dottedname = nodep->name() + "__DOT__"; // So always found diff --git a/test_regress/t/t_func_gen.pl b/test_regress/t/t_func_gen.pl new file mode 100755 index 000000000..7058e622f --- /dev/null +++ b/test_regress/t/t_func_gen.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_func_gen.v b/test_regress/t/t_func_gen.v new file mode 100644 index 000000000..bd55f1f61 --- /dev/null +++ b/test_regress/t/t_func_gen.v @@ -0,0 +1,21 @@ +module t (/*AUTOARG*/ + // Inputs + clk + ); + input clk; + genvar g; + generate + for (g=0; g<1; g++) + begin : picker + function [3:0] pick; + input [3:0] randnum; + pick = randnum+g[3:0]; + endfunction + always @(posedge clk) begin + if (pick(3)!=3+g[3:0]) $stop; + $write("*-* All Finished *-*\n"); + $finish; + end + end + endgenerate +endmodule