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Fix assignments of concatenation to queues and dynamic arrays (#5540)

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Ryszard Rozak 2024-10-15 13:35:59 +02:00 committed by GitHub
parent a3d0cc6522
commit 0dce97b09d
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3 changed files with 51 additions and 4 deletions
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14
src/V3Width.cpp
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@ -4622,9 +4622,12 @@ class WidthVisitor final : public VNVisitor {
for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
patp = VN_AS(patp->nextp(), PatMember)) {
patp->dtypep(arrayp->subDTypep());
AstNodeExpr* const valuep = patternMemberValueIterate(patp);
AstNodeExpr* const rhsp = patternMemberValueIterate(patp);
const bool rhsIsValue
= AstNode::computeCastable(rhsp->dtypep(), arrayp->subDTypep(), nullptr)
.isAssignable();
AstConsDynArray* const newap
= new AstConsDynArray{nodep->fileline(), true, valuep, false, newp};
= new AstConsDynArray{nodep->fileline(), rhsIsValue, rhsp, false, newp};
newap->dtypeFrom(arrayp);
newp = newap;
}
@ -4638,9 +4641,12 @@ class WidthVisitor final : public VNVisitor {
for (AstPatMember* patp = VN_AS(nodep->itemsp(), PatMember); patp;
patp = VN_AS(patp->nextp(), PatMember)) {
patp->dtypep(arrayp->subDTypep());
AstNodeExpr* const valuep = patternMemberValueIterate(patp);
AstNodeExpr* const rhsp = patternMemberValueIterate(patp);
const bool rhsIsValue
= AstNode::computeCastable(rhsp->dtypep(), arrayp->subDTypep(), nullptr)
.isAssignable();
AstConsQueue* const newap
= new AstConsQueue{nodep->fileline(), true, valuep, false, newp};
= new AstConsQueue{nodep->fileline(), rhsIsValue, rhsp, false, newp};
newap->dtypeFrom(arrayp);
newp = newap;
}

18
test_regress/t/t_queue_concat_assign.py Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/env python3
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2024 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
import vltest_bootstrap
test.scenarios('simulator')
test.compile()
test.execute()
test.passes()

23
test_regress/t/t_queue_concat_assign.v Normal file
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@ -0,0 +1,23 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2024 by Antmicro.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
initial begin
bit q1[$] = {1'b1};
bit q2[$];
bit [1:0] d1[] = {2'b10};
bit [1:0] d2[];
q2 = {q1};
if (q2[0] != 1) $stop;
d2 = {2'b11};
if (d2[0] != 2'b11) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule