diff --git a/.codacy.yml b/.codacy.yml
index b40076535..b3a99af01 100644
--- a/.codacy.yml
+++ b/.codacy.yml
@@ -1,3 +1,4 @@
---
exclude_paths:
+ - 'ci/build_verilator.sh'
- 'include/vltstd/**'
diff --git a/README.pod b/README.pod
index 011e1e70d..ddb5e4699 100644
--- a/README.pod
+++ b/README.pod
@@ -3,10 +3,14 @@
=pod
-=for html 
-=for html 
-=for html 
-=for html 
+=begin html
+
+
+
+
+
+
+=end html
=head1 NAME
diff --git a/ci/build_verilator.sh b/ci/build_verilator.sh
index 338e5e503..cd1d7d558 100755
--- a/ci/build_verilator.sh
+++ b/ci/build_verilator.sh
@@ -37,8 +37,8 @@ echo "Found Verilator rev ${VERILATOR_REV}"
CACHED_REV_FILE=${VERILATOR_CACHE}/.rev.txt
-if [[ ! -f ${CACHED_REV_FILE} || \
- $(< ${CACHED_REV_FILE}) != ${VERILATOR_REV} ]]; then
+if [[ ! -f "${CACHED_REV_FILE}" || \
+ $(< "${CACHED_REV_FILE}") != "${VERILATOR_REV}" ]]; then
echo "Building Verilator"
# Unsure why Travis monkies with the capitalization of the stage name, but it does
@@ -47,18 +47,18 @@ if [[ ! -f ${CACHED_REV_FILE} || \
echo "WARNING: Building Verilator in Travis build stage other than \"Build verilator\": ${TRAVIS_BUILD_STAGE_NAME}"
fi
- cd ${VERILATOR_ROOT}
+ cd "${VERILATOR_ROOT}"
autoconf && ./configure ${VERILATOR_CONFIG_FLAGS} && make -j ${VERILATOR_NUM_JOBS}
# Copy the Verilator build artifacts
mkdir -p "${VERILATOR_CACHE}"
- rm -rf "${VERILATOR_CACHE}/*"
+ rm -rf ${VERILATOR_CACHE}/*
cp bin/*bin* "${VERILATOR_CACHE}"
# Remember the Git revision
- echo ${VERILATOR_REV} > ${CACHED_REV_FILE}
+ echo "${VERILATOR_REV}" > "${CACHED_REV_FILE}"
else
echo "Using cached Verilator"
cd "${VERILATOR_ROOT}"
# Create include/verilated_config.h and maybe other things
autoconf && ./configure ${VERILATOR_CONFIG_FLAGS}
- cp "${VERILATOR_CACHE}/*" bin
+ cp ${VERILATOR_CACHE}/* bin
fi
diff --git a/src/V3Life.cpp b/src/V3Life.cpp
index 9d2518b14..a11647dc9 100644
--- a/src/V3Life.cpp
+++ b/src/V3Life.cpp
@@ -377,14 +377,13 @@ private:
m_lifep = condLifep;
iterateAndNextNull(nodep->precondsp());
iterateAndNextNull(nodep->condp());
- m_lifep = prevLifep;
}
{
m_lifep = bodyLifep;
iterateAndNextNull(nodep->bodysp());
iterateAndNextNull(nodep->incsp());
- m_lifep = prevLifep;
}
+ m_lifep = prevLifep;
UINFO(4," joinfor"<lifeToAbove();
diff --git a/src/V3ProtectLib.cpp b/src/V3ProtectLib.cpp
index 7f008d075..136532dac 100644
--- a/src/V3ProtectLib.cpp
+++ b/src/V3ProtectLib.cpp
@@ -394,7 +394,6 @@ class ProtectVisitor : public AstNVisitor {
}
void handleInput(AstVar* varp) {
- FileLine* fl = varp->fileline();
m_modPortsp->addNodep(varp->cloneTree(false));
}
@@ -433,7 +432,9 @@ class ProtectVisitor : public AstNVisitor {
explicit ProtectVisitor(AstNode* nodep):
m_vfilep(NULL), m_cfilep(NULL), m_modPortsp(NULL),
m_comboPortsp(NULL), m_seqPortsp(NULL), m_comboIgnorePortsp(NULL), m_comboDeclsp(NULL),
- m_seqDeclsp(NULL), m_tmpDeclsp(NULL), m_hashValuep(NULL), m_clkSensp(NULL),
+ m_seqDeclsp(NULL), m_tmpDeclsp(NULL), m_hashValuep(NULL),
+ m_comboParamsp(NULL),
+ m_clkSensp(NULL),
m_comboIgnoreParamsp(NULL), m_seqParamsp(NULL), m_nbAssignsp(NULL), m_seqAssignsp(NULL),
m_comboAssignsp(NULL), m_cHashValuep(NULL), m_cComboParamsp(NULL), m_cComboInsp(NULL),
m_cComboOutsp(NULL), m_cSeqParamsp(NULL), m_cSeqClksp(NULL), m_cSeqOutsp(NULL),
diff --git a/test_regress/t/t_clk_2in.cpp b/test_regress/t/t_clk_2in.cpp
index 182de5b45..6b637657e 100644
--- a/test_regress/t/t_clk_2in.cpp
+++ b/test_regress/t/t_clk_2in.cpp
@@ -23,7 +23,7 @@ void clockit(int clk1, int clk0) {
topp->c0 = clk0;
#endif
#ifdef TEST_VERBOSE
- printf("[%d] c1=%u c0=%u\n", main_time, clk1, clk0);
+ printf("[%u] c1=%d c0=%d\n", main_time, clk1, clk0);
#endif
topp->eval();
main_time++;
diff --git a/test_regress/t/t_dpi_context_c.cpp b/test_regress/t/t_dpi_context_c.cpp
index 9035d7af0..bedf3f85d 100644
--- a/test_regress/t/t_dpi_context_c.cpp
+++ b/test_regress/t/t_dpi_context_c.cpp
@@ -99,7 +99,7 @@ int dpic_save(int value) {
int i;
} vp;
- vp.i = value;
+ vp.i = value; if (vp.i) { }
if (svPutUserData(scope, &Dpic_Unique, vp.ptr)) {
printf("%%Warning: svPutUserData failed\n");
return 0;
diff --git a/test_regress/t/t_dpi_export_c.cpp b/test_regress/t/t_dpi_export_c.cpp
index 2b75bb11f..dba8b9901 100644
--- a/test_regress/t/t_dpi_export_c.cpp
+++ b/test_regress/t/t_dpi_export_c.cpp
@@ -76,6 +76,7 @@ extern "C" {
printf("%%Error: %s:%d:", __FILE__,__LINE__); \
union { type a; long long l; } u; \
u.l = 0; u.a = got; \
+ if (u.a) { } /*not unused*/ \
printf(" GOT = %" T_PRI64 "x", u.l); \
u.l = 0; u.a = exp; \
printf(" EXP = %" T_PRI64 "x\n", u.l); \
diff --git a/test_regress/t/t_mem_slot.cpp b/test_regress/t/t_mem_slot.cpp
index 61592000e..4c6bded5f 100644
--- a/test_regress/t/t_mem_slot.cpp
+++ b/test_regress/t/t_mem_slot.cpp
@@ -8,7 +8,7 @@ unsigned int Array[3];
unsigned int StepSim(Vt_mem_slot *sim, unsigned int slot, unsigned int bit, unsigned int val, unsigned int rslot) {
#ifdef TEST_VERBOSE
- printf("StepSim: slot=%d bit=%d val=%d rslot=%d\n", slot, bit, val, rslot);
+ printf("StepSim: slot=%u bit=%u val=%u rslot=%u\n", slot, bit, val, rslot);
#endif
sim->SlotIdx = slot;