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Fix supporting begin_keywords 1364-2001-noconfig
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Wilson Snyder
parent
6adda241c9
commit
0abf18f618
@ -78,7 +78,7 @@ static double lexParseDouble(FileLine* fl, const char* textp, size_t length) {
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%a 15000
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%o 25000
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%s V95 V01 V05 S05 S09 S12 S17
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%s V95 V01NC V01C V05 S05 S09 S12 S17
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%s STRING ATTRMODE TABLE
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%s VA5 SAX VLT
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%s SYSCHDR SYSCINT SYSCIMP SYSCIMPH SYSCCTOR SYSCDTOR
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@ -155,7 +155,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/************************************************************************/
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/* Verilog 1995 */
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<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
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<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
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{ws} { FL_FWD; FL_BRK; } /* otherwise ignore white-space */
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{crnl} { FL_FWD; FL_BRK; } /* Count line numbers */
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/* Extensions to Verilog set, some specified by PSL */
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@ -395,7 +395,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* Verilog 2001 */
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<V01,V05,VA5,S05,S09,S12,S17,SAX>{
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<V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
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/* System Tasks */
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"$signed" { FL; return yD_SIGNED; }
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"$unsigned" { FL; return yD_UNSIGNED; }
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@ -412,6 +412,10 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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"showcancelled" { FL; return yaTIMINGSPEC; }
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"signed" { FL; return ySIGNED; }
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"unsigned" { FL; return yUNSIGNED; }
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}
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/* Verilog 2001 Config */
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<V01C,V05,VA5,S05,S09,S12,S17,SAX>{
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/* Generic unsupported keywords */
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"cell" { ERROR_RSVD_WORD("Verilog 2001-config"); }
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"config" { ERROR_RSVD_WORD("Verilog 2001-config"); }
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@ -606,7 +610,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/* No new keywords */
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/* Default PLI rule */
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<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
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<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
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"$"[a-zA-Z_$][a-zA-Z0-9_$]* { string str (yytext, yyleng);
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yylval.strp = PARSEP->newString(AstNode::encodeName(str));
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FL; return yaD_PLI;
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@ -710,7 +714,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/* Meta comments */
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/* Converted from //{cmt}verilator ...{cmt} by preprocessor */
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<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
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<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
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"/*verilator"{ws}*"*/" { FL_FWD; FL_BRK; } /* Ignore empty comments, may be `endif // verilator */
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"/*verilator clock_enable*/" { FL; return yVL_CLOCK_ENABLE; }
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"/*verilator clocker*/" { FL; return yVL_CLOCKER; }
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@ -750,7 +754,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/************************************************************************/
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/* Single character operator thingies */
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<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
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<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
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"{" { FL; return yytext[0]; }
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"}" { FL; return yytext[0]; }
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"!" { FL; return yytext[0]; }
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@ -784,7 +788,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/* Operators and multi-character symbols */
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/* Verilog 1995 Operators */
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<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
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<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
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"&&" { FL; return yP_ANDAND; }
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"||" { FL; return yP_OROR; }
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"<=" { FL; return yP_LTE; }
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@ -806,7 +810,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* Verilog 2001 Operators */
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<V01,V05,VA5,S05,S09,S12,S17,SAX>{
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<V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
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"<<<" { FL; return yP_SLEFT; }
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">>>" { FL; return yP_SSRIGHT; }
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"**" { FL; return yP_POW; }
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@ -858,7 +862,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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}
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/* Identifiers and numbers */
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<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
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<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
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{escid} { FL; yylval.strp = PARSEP->newString
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(AstNode::encodeName(string(yytext+1))); // +1 to skip the backslash
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return yaID__LEX;
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@ -936,7 +940,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/************************************************************************/
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/* Attributes */
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/* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
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<V95,V01,V05,VA5,S05,S09,S12,S17,SAX>{
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<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX>{
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"(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } /* Doesn't match (*), but (* attr_spec */
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}
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@ -956,7 +960,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/* Common for all SYSC header states */
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/* OPTIMIZE: we return one per line, make it one for the entire block */
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/* If add to this list also add to V3LanguageWords.h */
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<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
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<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX,VLT,SYSCHDR,SYSCINT,SYSCIMP,SYSCIMPH,SYSCCTOR,SYSCDTOR,IGNORE>{
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"`accelerate" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
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"`autoexpand_vectornets" { FL_FWD; FL_BRK; } // Verilog-XL compatibility
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"`celldefine" { FL_FWD; PARSEP->lexFileline()->celldefineOn(true); FL_BRK; }
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@ -1004,8 +1008,8 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/* See also setLanguage below */
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"`begin_keywords"[ \t]*\"1364-1995\" { FL_FWD; yy_push_state(V95); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
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"`begin_keywords"[ \t]*\"1364-2001\" { FL_FWD; yy_push_state(V01); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
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"`begin_keywords"[ \t]*\"1364-2001-noconfig\" { FL_FWD; yy_push_state(V01); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
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"`begin_keywords"[ \t]*\"1364-2001\" { FL_FWD; yy_push_state(V01C); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
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"`begin_keywords"[ \t]*\"1364-2001-noconfig\" { FL_FWD; yy_push_state(V01NC); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
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"`begin_keywords"[ \t]*\"1364-2005\" { FL_FWD; yy_push_state(V05); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
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"`begin_keywords"[ \t]*\"VAMS[-0-9.]*\" { FL_FWD; yy_push_state(VA5); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
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"`begin_keywords"[ \t]*\"1800-2005\" { FL_FWD; yy_push_state(S05); PARSEP->lexPushKeywords(YY_START); FL_BRK; }
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@ -1052,7 +1056,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
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/************************************************************************/
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/* Default rules - leave last */
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<V95,V01,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
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<V95,V01NC,V01C,V05,VA5,S05,S09,S12,S17,SAX,VLT>{
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"`"[a-zA-Z_0-9]+ { FL; V3ParseImp::lexErrorPreprocDirective(yylval.fl, yytext); FL_BRK; }
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"//"[^\n]* { FL_FWD; FL_BRK; } /* throw away single line comments */
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. { FL; return yytext[0]; } /* return single char ops. */
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@ -11,7 +11,8 @@ module t (/*AUTOARG*/
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input clk;
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v95 v95 ();
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v01 v01 ();
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v01nc v01nc ();
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v01c v01c ();
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v05 v05 ();
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s05 s05 ();
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s09 s09 ();
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@ -31,26 +32,37 @@ module v95;
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endmodule
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`end_keywords
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`begin_keywords "1364-2001-noconfig"
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module v01nc;
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localparam g = 0;
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integer instance; initial instance = 1;
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endmodule
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`end_keywords
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`begin_keywords "1364-2001"
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module v01;
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module v01c;
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localparam g = 0;
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integer bit; initial bit = 1;
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endmodule
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`end_keywords
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`begin_keywords "1364-2005"
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module v05;
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uwire w;
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integer final; initial final = 1;
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endmodule
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`end_keywords
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`begin_keywords "1800-2005"
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module s05;
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bit b;
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integer global; initial global = 1;
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endmodule
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`end_keywords
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`begin_keywords "1800-2009"
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module s09;
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bit b;
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integer soft; initial soft = 1;
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endmodule
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`end_keywords
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