diff --git a/bin/verilator b/bin/verilator index b3d6da8c2..9fe7c4a2f 100755 --- a/bin/verilator +++ b/bin/verilator @@ -234,6 +234,7 @@ descriptions in the next sections for more information. --sc Create SystemC output --sp Create SystemPerl output --stats Create statistics file + -sv Enable SystemVerilog parsing --top-module Name of top level input module --trace Enable waveform creation --trace-depth Depth of tracing @@ -600,6 +601,12 @@ Specifies SystemPerl output mode; see also --cc and -sc. Creates a dump file with statistics on the design in {prefix}__stats.txt. +=item -sv + +Specifies SystemVerilog language features should be enabled; equivalent to +"--language 1800-2005". This option is selected by default, it exists for +compatibility with other simulators. + =item --top-module I When the input Verilog contains more than one top level module, specifies diff --git a/src/V3Options.cpp b/src/V3Options.cpp index 0c471253a..01542d0ca 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -677,9 +677,10 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) { else if ( onoff (sw, "-psl", flag/*ref*/) ) { m_psl = flag; } else if ( onoff (sw, "-public", flag/*ref*/) ) { m_public = flag; } else if ( !strcmp (sw, "-sc") ) { m_outFormatOk = true; m_systemC = true; m_systemPerl = false; } - else if ( !strcmp (sw, "-sp") ) { m_outFormatOk = true; m_systemC = true; m_systemPerl = true; } else if ( onoff (sw, "-skip-identical", flag/*ref*/) ) { m_skipIdentical = flag; } + else if ( !strcmp (sw, "-sp") ) { m_outFormatOk = true; m_systemC = true; m_systemPerl = true; } else if ( onoff (sw, "-stats", flag/*ref*/) ) { m_stats = flag; } + else if ( !strcmp (sw, "-sv") ) { m_language = V3LangCode::L1800_2005; } else if ( onoff (sw, "-trace", flag/*ref*/) ) { m_trace = flag; } else if ( onoff (sw, "-trace-dups", flag/*ref*/) ) { m_traceDups = flag; } else if ( onoff (sw, "-underline-zero", flag/*ref*/) ) { m_underlineZero = flag; } // Undocumented, old Verilator-2