diff --git a/test_regress/t/t_fork_none_var.pl b/test_regress/t/t_fork_none_var.pl
new file mode 100755
index 000000000..3407291f9
--- /dev/null
+++ b/test_regress/t/t_fork_none_var.pl
@@ -0,0 +1,25 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2023 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ["--exe --main --timing"],
+    make_main => 0,
+    fails => $Self->{vlt_all},  # issue #4493
+    );
+
+# issue #4493
+#execute(
+#    check_finished => 1,
+#    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_fork_none_var.v b/test_regress/t/t_fork_none_var.v
new file mode 100644
index 000000000..3b568b085
--- /dev/null
+++ b/test_regress/t/t_fork_none_var.v
@@ -0,0 +1,47 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+
+   logic [3:0] m_mask;
+
+   initial begin
+      int i;
+      int n = 4;
+      m_mask = 0;
+      fork
+         begin
+            fork
+               begin
+                  fork
+                     begin
+                        for(i = 0; i < n; i++) begin
+                           fork
+                              automatic int k = i;
+                              begin
+                                 // issue #4493
+                                 $display("[%0t] start %0d", $time, k);
+                                 // UVM's arb_sequence_q[is_relevant_entries[k]].wait_for_relevant();
+                                 m_mask[k] = 1;
+                                 #1;
+                              end
+                           join_none
+                           wait (m_mask[i]);
+                        end
+                     end
+                  join_any
+               end
+            join_any
+         end
+      join
+
+      if (m_mask != {4{1'b1}}) $stop;
+
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule