When warnings are disabled on signals that are flattened out, disable

the warnings on the signal(s) that replace it.

Changes

@@ -3,6 +3,11 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.6***
+
+***  When warnings are disabled on signals that are flattened out, disable
+     the warnings on the signal(s) that replace it.
+
 * Verilator 3.670 2008/07/23
 
 **   Add --x-assign=fast option, and make it the default.

MANIFEST.SKIP

@@ -16,6 +16,7 @@
 /obj_dbg/
 /obj_opt/
 /INCA_libs/
+/cov_work/
 /logs/
 Makefile
 src/Makefile_obj

bin/verilator

@@ -2200,7 +2200,7 @@ From the sc_main.cpp file, you'd then:
 
     #include "Vour.h"
     #include "Vour_our.h"
-    top->v.publicSetBool(value);
+    top->v->publicSetBool(value);
 
 See additional notes under the /*verilator public*/ section.
 
@@ -2235,7 +2235,7 @@ From the sc_main.cpp file, you'd then:
 
     #include "Vour.h"
     #include "Vour_our.h"
-    cout << "clock is " << top->v.clk << endl;
+    cout << "clock is " << top->v->clk << endl;
 
 In this example, clk is a bool you can read or set as any other variable.
 The value of normal signals may be set, though clocks shouldn't be changed

src/V3Error.cpp

@@ -153,13 +153,23 @@ ostream& operator<<(ostream& os, FileLine* fileline) {
     return(os);
 }
 
-bool FileLine::warnIsOff(V3ErrorCode code) {
+bool FileLine::warnIsOff(V3ErrorCode code) const {
     if (m_warnOff.test(code)) return true;
     // UNOPTFLAT implies UNOPT
     if (code==V3ErrorCode::UNOPT && m_warnOff.test(V3ErrorCode::UNOPTFLAT)) return true;
     return false;
 }
 
+void FileLine::warnStateInherit(const FileLine& from) {
+    // Any warnings that are off in "from", become off in "this".
+    for (int codei=V3ErrorCode::FIRST_WARN; codei<V3ErrorCode::MAX; codei++) {
+	V3ErrorCode code = (V3ErrorCode)codei;
+	if (from.warnIsOff(code)) {
+	    this->warnOff(code, true);
+	}
+    }
+}
+
 void FileLine::v3errorEnd(ostringstream& str) {
     if (this && m_lineno) {
 	ostringstream nsstr;

src/V3Error.h

@@ -222,9 +222,10 @@ public:
     const string profileFuncname() const;
     void warnOff(V3ErrorCode code, bool flag) { m_warnOff.set(code,flag); }	// Turn on/off warning messages on this line.
     bool warnOff(const string& code, bool flag);  // Returns 1 if ok
-    bool warnIsOff(V3ErrorCode code);
+    bool warnIsOff(V3ErrorCode code) const;
     void warnLintOff(bool flag);
     void warnStateFrom(const FileLine& from) { m_warnOff=from.m_warnOff; }
+    void warnStateInherit(const FileLine& from);
     void warnResetDefault() { warnStateFrom(s_defaultFileLine); }
 
     void	v3errorEnd(ostringstream& str);

src/V3Inline.cpp

@@ -172,6 +172,8 @@ private:
 		    m_modp->addStmtp(new AstAssignAlias(nodep->fileline(),
 							new AstVarRef(nodep->fileline(), nodep, true),
 							new AstVarRef(nodep->fileline(), exprvarrefp->varp(), false)));
+		    nodep->fileline()->warnStateInherit(exprvarrefp->varp()->fileline());
+		    exprvarrefp->varp()->fileline()->warnStateInherit(nodep->fileline());
 		}
 	    }
 	    // Variable under the inline cell, need to rename to avoid conflicts

src/V3Link.cpp

@@ -164,6 +164,7 @@ private:
 		    if ((findvarp->isIO() && nodep->isSignal())
 			|| (findvarp->isSignal() && nodep->isIO())) {
 			findvarp->combineType(nodep);
+			findvarp->fileline()->warnStateInherit(nodep->fileline());
 			nodep->unlinkFrBack()->deleteTree(); nodep=NULL;
 		    } else {
 			nodep->v3error("Duplicate declaration of signal: "<<nodep->prettyName());

test_regress/.gitignore

@@ -2,9 +2,11 @@
 obj_dir
 vcs.key
 csrc
+cov_work
 simv*
 simx*
 *.log
+*.key
 ncverilog.*
 INCA_libs
 logs

test_regress/Makefile

@@ -70,5 +70,5 @@ random_forever:
 ######################################################################
 maintainer-copy::
 clean mostlyclean distclean maintainer-clean::
-	-rm -rf obj_dir simv* simx* csrc INCA_libs *.log logs
+	-rm -rf obj_dir simv* simx* csrc cov_work INCA_libs *.log *.key logs
 

test_regress/t/t_lint_inherit.pl

@@ -0,0 +1,13 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+ok(1);
+1;

test_regress/t/t_lint_inherit.v

@@ -0,0 +1,60 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2008 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   q,
+   // Inputs
+   clk, d
+   );
+   input clk;
+   input d;
+   output wire [1:0] q;
+
+   // This demonstrates how warning disables should be propagated across module boundaries.
+
+   m1 m1 (/*AUTOINST*/
+	  // Outputs
+	  .q				(q[1:0]),
+	  // Inputs
+	  .clk				(clk),
+	  .d				(d));
+endmodule
+
+module m1
+  (
+   input clk,
+   input d,
+   output wire [1:0] q
+   );
+   
+   m2 m2 (/*AUTOINST*/
+	  // Outputs
+	  .q				(q[1:0]),
+	  // Inputs
+	  .clk				(clk),
+	  .d				(d));
+endmodule
+
+module m2
+  (
+   input clk,
+   input d,
+   // Due to bug the below disable used to be ignored.
+   // verilator lint_off UNOPT
+   output reg [1:0] q
+   // verilator lint_on UNOPT
+   );
+   
+   always @* begin
+      q[1] = d;
+   end
+
+   always @* begin
+      q[0] = q[1];
+   end
+
+endmodule
+