From 016e630ecfcaf10aa3e2e290f019ae6744ddfa54 Mon Sep 17 00:00:00 2001
From: Krzysztof Bieganski <kbieganski@antmicro.com>
Date: Wed, 20 Dec 2023 18:12:17 +0100
Subject: [PATCH] Refine dynamic NBA condition (#4773)

Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com>
---
 src/V3Fork.cpp                     |  4 +++-
 test_regress/t/t_assigndly_task.pl | 17 +++++++++++++++++
 test_regress/t/t_assigndly_task.v  | 22 ++++++++++++++++++++++
 3 files changed, 42 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_assigndly_task.pl
 create mode 100644 test_regress/t/t_assigndly_task.v

diff --git a/src/V3Fork.cpp b/src/V3Fork.cpp
index 117305151..f0f9e3e2f 100644
--- a/src/V3Fork.cpp
+++ b/src/V3Fork.cpp
@@ -414,7 +414,9 @@ class DynScopeVisitor final : public VNVisitor {
     void visit(AstAssignDly* nodep) override {
         if (m_procp && !nodep->user2()  // Unhandled AssignDly in function/task
             && nodep->lhsp()->exists(  // And writes to a local variable
-                [](AstVarRef* refp) { return refp->varp()->isFuncLocal(); })) {
+                [](AstVarRef* refp) {
+                    return refp->access().isWriteOrRW() && refp->varp()->isFuncLocal();
+                })) {
             nodep->user2(true);
             // Put it in a fork to prevent lifetime issues with the local
             AstFork* const forkp = new AstFork{nodep->fileline(), "", nullptr};
diff --git a/test_regress/t/t_assigndly_task.pl b/test_regress/t/t_assigndly_task.pl
new file mode 100755
index 000000000..da2e37bda
--- /dev/null
+++ b/test_regress/t/t_assigndly_task.pl
@@ -0,0 +1,17 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_assigndly_task.v b/test_regress/t/t_assigndly_task.v
new file mode 100644
index 000000000..3d51a7ad6
--- /dev/null
+++ b/test_regress/t/t_assigndly_task.v
@@ -0,0 +1,22 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2023 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (
+  input clk,
+  input [7:0] d,
+  input [2:0] a,
+  output [7:0] q
+);
+  always_ff @(posedge clk) tick(a);
+
+  logic [7:0] d_ = d;
+  logic [7:0] q_;
+  assign q = q_;
+
+  task automatic tick(logic [2:0] a);
+    q_[a] <= d_[a];
+  endtask
+endmodule