diff --git a/Changes b/Changes index 281c7544f..3d98cb9da 100644 --- a/Changes +++ b/Changes @@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks! *** Ignore old standard(ish) Verilog-XL defines. [by Stefan Thiede] +*** Allow /**/ comments in -f option files. [Stefan Thiede] + **** Fix "always @ ((a) or (b))" syntax error. [by Niranjan Prabhu] **** Fix "output reg name=expr;" syntax error. [Martin Scharrer] diff --git a/src/V3Options.cpp b/src/V3Options.cpp index ef40e43ff..343fcc030 100644 --- a/src/V3Options.cpp +++ b/src/V3Options.cpp @@ -729,16 +729,31 @@ void V3Options::parseOptsFile(FileLine* fl, const string& filename) { string whole_file; string::size_type pos; + bool inCmt = false; while (!ifp->eof()) { string line; getline(*ifp, line); // Strip simple comments - if ((pos=line.find("//")) != string::npos) { - line.erase(pos); + string oline; + for (string::const_iterator pos = line.begin(); pos != line.end(); pos++) { + if (inCmt) { + if (*pos=='*' && *(pos+1)=='/') { + inCmt = false; + pos++; + } + } else if (*pos=='/' && *(pos+1)=='/') { + break; // Ignore to EOL + } else if (*pos=='/' && *(pos+1)=='*') { + inCmt = true; + pos++; + } else { + oline += *pos; + } } - whole_file += line + " "; + whole_file += oline + " "; } whole_file += "\n"; // So string match below is simplified + if (inCmt) fl->v3error("Unterminated /* comment inside -f file."); fl = new FileLine(filename, 0); diff --git a/test_regress/t/t_flag_f.pl b/test_regress/t/t_flag_f.pl new file mode 100755 index 000000000..059006dd0 --- /dev/null +++ b/test_regress/t/t_flag_f.pl @@ -0,0 +1,19 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; } +# $Id$ +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2008 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# General Public License or the Perl Artistic License. + +compile ( + v_flags2 => ["-f t/t_flag_f.vc"], + ); + +execute ( + check_finished=>1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_flag_f.v b/test_regress/t/t_flag_f.v new file mode 100644 index 000000000..04eaec8af --- /dev/null +++ b/test_regress/t/t_flag_f.v @@ -0,0 +1,18 @@ +// $Id$ +// DESCRIPTION: Verilator: Verilog Test module + +module t; + initial begin +`ifndef GOT_DEF1 + $write("%%Error: NO GOT_DEF1\n"); $stop; +`endif +`ifndef GOT_DEF2 + $write("%%Error: NO GOT_DEF2\n"); $stop; +`endif +`ifdef NON_DEF + $write("%%Error: NON_DEF\n"); $stop; +`endif + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule diff --git a/test_regress/t/t_flag_f.vc b/test_regress/t/t_flag_f.vc new file mode 100644 index 000000000..3ba204041 --- /dev/null +++ b/test_regress/t/t_flag_f.vc @@ -0,0 +1,10 @@ + ++define+GOT_DEF1 + + // -DNON_DEF + /* + +define+NON_DEF + */ + ++define+GOT_DEF2=1 +