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Fix overly aggressive --protect-lib check
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13569ed98b
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@ -65,6 +65,7 @@ class ProtectVisitor : public AstNVisitor {
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AstTextBlock* m_cIgnoreParamsp; // Combo ignore parameter list
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AstTextBlock* m_cIgnoreParamsp; // Combo ignore parameter list
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string m_libName;
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string m_libName;
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string m_topName;
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string m_topName;
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bool m_foundTop; // Have seen the top module
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// VISITORS
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// VISITORS
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virtual void visit(AstNetlist* nodep) {
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virtual void visit(AstNetlist* nodep) {
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@ -78,7 +79,11 @@ class ProtectVisitor : public AstNVisitor {
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}
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}
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virtual void visit(AstNodeModule* nodep) {
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virtual void visit(AstNodeModule* nodep) {
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UASSERT_OBJ(!nodep->nextp(), nodep, "Multiple root modules");
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if (!nodep->isTop()) {
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return;
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} else {
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UASSERT_OBJ(!m_foundTop, nodep, "Multiple root modules");
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}
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FileLine* fl = nodep->fileline();
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FileLine* fl = nodep->fileline();
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createSvFile(fl);
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createSvFile(fl);
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createCppFile(fl);
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createCppFile(fl);
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@ -88,6 +93,7 @@ class ProtectVisitor : public AstNVisitor {
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V3Hash hash = V3Hashed::uncachedHash(m_cfilep);
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V3Hash hash = V3Hashed::uncachedHash(m_cfilep);
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m_hashValuep->addText(fl, cvtToStr(hash.fullValue())+";\n");
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m_hashValuep->addText(fl, cvtToStr(hash.fullValue())+";\n");
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m_cHashValuep->addText(fl, cvtToStr(hash.fullValue())+";\n");
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m_cHashValuep->addText(fl, cvtToStr(hash.fullValue())+";\n");
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m_foundTop = true;
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}
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}
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void addComment(AstTextBlock* txtp, FileLine* fl, const string& comment) {
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void addComment(AstTextBlock* txtp, FileLine* fl, const string& comment) {
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@ -439,7 +445,7 @@ class ProtectVisitor : public AstNVisitor {
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m_comboAssignsp(NULL), m_cHashValuep(NULL), m_cComboParamsp(NULL), m_cComboInsp(NULL),
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m_comboAssignsp(NULL), m_cHashValuep(NULL), m_cComboParamsp(NULL), m_cComboInsp(NULL),
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m_cComboOutsp(NULL), m_cSeqParamsp(NULL), m_cSeqClksp(NULL), m_cSeqOutsp(NULL),
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m_cComboOutsp(NULL), m_cSeqParamsp(NULL), m_cSeqClksp(NULL), m_cSeqOutsp(NULL),
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m_cIgnoreParamsp(NULL), m_libName(v3Global.opt.protectLib()),
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m_cIgnoreParamsp(NULL), m_libName(v3Global.opt.protectLib()),
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m_topName(v3Global.opt.prefix())
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m_topName(v3Global.opt.prefix()), m_foundTop(false)
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{
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{
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iterate(nodep);
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iterate(nodep);
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}
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}
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@ -3,30 +3,30 @@
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// without warranty, 2019 by Todd Strader.
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// without warranty, 2019 by Todd Strader.
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module secret (
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module secret (
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input [31:0] accum_in,
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input [31:0] accum_in,
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output wire [31:0] accum_out,
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output wire [31:0] accum_out,
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input accum_bypass,
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input accum_bypass,
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output [31:0] accum_bypass_out,
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output [31:0] accum_bypass_out,
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input s1_in,
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input s1_in,
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output logic s1_out,
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output logic s1_out,
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input [1:0] s2_in,
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input [1:0] s2_in,
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output logic [1:0] s2_out,
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output logic [1:0] s2_out,
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input [7:0] s8_in,
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input [7:0] s8_in,
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output logic [7:0] s8_out,
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output logic [7:0] s8_out,
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input [32:0] s33_in,
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input [32:0] s33_in,
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output logic [32:0] s33_out,
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output logic [32:0] s33_out,
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input [63:0] s64_in,
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input [63:0] s64_in,
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output logic [63:0] s64_out,
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output logic [63:0] s64_out,
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input [64:0] s65_in,
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input [64:0] s65_in,
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output logic [64:0] s65_out,
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output logic [64:0] s65_out,
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input [128:0] s129_in,
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input [128:0] s129_in,
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output logic [128:0] s129_out,
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output logic [128:0] s129_out,
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input [3:0] [31:0] s4x32_in,
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input [3:0] [31:0] s4x32_in,
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output logic [3:0] [31:0] s4x32_out,
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output logic [3:0] [31:0] s4x32_out,
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input clk);
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input clk);
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logic [31:0] secret_accum_q = 0;
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logic [31:0] secret_accum_q = 0;
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logic [31:0] secret_value = 7;
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logic [31:0] secret_value = 7;
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initial $display("created %m");
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initial $display("created %m");
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@ -39,13 +39,14 @@ module secret (
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s1_out = s1_in;
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s1_out = s1_in;
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s2_out = s2_in;
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s2_out = s2_in;
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s8_out = s8_in;
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s8_out = s8_in;
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s33_out = s33_in;
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s64_out = s64_in;
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s64_out = s64_in;
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s65_out = s65_in;
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s65_out = s65_in;
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s129_out = s129_in;
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s129_out = s129_in;
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s4x32_out = s4x32_in;
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s4x32_out = s4x32_in;
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end
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end
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sub sub (.sub_in(s33_in), .sub_out(s33_out));
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// Test sequential path
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// Test sequential path
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assign accum_out = secret_accum_q;
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assign accum_out = secret_accum_q;
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@ -55,3 +56,13 @@ module secret (
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final $display("destroying %m");
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final $display("destroying %m");
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endmodule
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endmodule
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module sub (
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input [32:0] sub_in,
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output [32:0] sub_out);
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/*verilator no_inline_module*/
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assign sub_out = sub_in;
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endmodule
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