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28 lines
622 B
Systemverilog
28 lines
622 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/);
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class Cls;
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typedef enum {A = 10, B = 20, C = 30} en_t;
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local int m_loc = 2;
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protected int m_prot = B;
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endclass
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initial begin
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Cls c;
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if (c.A != 10) $stop;
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c = new;
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if (c.m_loc != 2) $stop;
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c.m_loc = 10;
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if (c.m_loc != 10) $stop;
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if (c.m_prot != 20) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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