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20 lines
437 B
Systemverilog
20 lines
437 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 Krzysztof Boronski.
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// SPDX-License-Identifier: CC0-1.0
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int i = 0;
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function int postincrement_i;
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return i++;
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endfunction
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module t;
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initial begin
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int arr [1:0] = {0, 0};
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i = 0;
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$display("Value: %d", arr[postincrement_i()]++);
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end
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endmodule
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