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36 lines
1.4 KiB
Python
36 lines
1.4 KiB
Python
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#!/usr/bin/env python3
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2024 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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import vltest_bootstrap
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test.scenarios('simulator')
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test.top_filename = "t/t_inst_tree.v"
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out_filename = test.obj_dir + "/V" + test.name + ".tree.json"
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test.compile(v_flags2=["--no-json-edit-nums", test.t_dir + "/" + test.name + ".vlt"])
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if test.vlt_all:
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test.file_grep(out_filename,
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r'{"type":"MODULE","name":"l1",.*"loc":"f,56:[^"]*",.*"origName":"l1"')
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test.file_grep(out_filename,
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r'{"type":"MODULE","name":"l2",.*"loc":"f,62:[^"]*",.*"origName":"l2"')
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test.file_grep(out_filename,
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r'{"type":"MODULE","name":"l3",.*"loc":"f,69:[^"]*",.*"origName":"l3"')
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test.file_grep(out_filename,
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r'{"type":"MODULE","name":"l4",.*"loc":"f,76:[^"]*",.*"origName":"l4"')
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test.file_grep(out_filename,
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r'{"type":"MODULE","name":"l5__P1",.*"loc":"f,83:[^"]*",.*"origName":"l5"')
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test.file_grep(out_filename,
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r'{"type":"MODULE","name":"l5__P2",.*"loc":"f,83:[^"]*",.*"origName":"l5"')
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test.execute(expect=r"\] (%m|.*t\.ps): Clocked", )
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test.passes()
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