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20 lines
410 B
Systemverilog
20 lines
410 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic x;
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sub s(x);
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initial #1 x = 1;
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endmodule
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module sub(input x);
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initial fork begin
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@x;
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$write("*-* All Finished *-*\n");
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$finish;
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end join_any
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endmodule
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