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70 lines
1.9 KiB
Systemverilog
70 lines
1.9 KiB
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Use this file as a template for submitting bugs, etc.
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// This module takes a single clock input, and should either
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// $write("*-* All Finished *-*\n");
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// $finish;
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// on success, or $stop.
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//
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// The code as shown applies a random vector to the Test
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// module, then calculates a CRC on the Test module's outputs.
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//
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// **If you do not wish for your code to be released to the public
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// please note it here, otherwise:**
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc = 0;
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reg [31:0] istr;
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string sstr;
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string v;
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// Test loop
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always @ (posedge clk) begin
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`ifdef TEST_VERBOSE
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$write("[%0t] cyc==%0d istr='%s' sstr='%s'\n", $time, cyc, istr, sstr);
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`endif
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cyc <= cyc + 1;
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sstr <= string'(istr); // Note takes another cycle
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if (cyc < 10) begin
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istr <= 32'h00_00_00_00;
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end
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else if (cyc == 13) begin
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// These displays are needed to check padding of %s
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$display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr);
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if (sstr.len() != 0) $stop;
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if (sstr != "") $stop;
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end
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else if (cyc == 20) begin
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istr <= 32'h00_00_41_00;
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end
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else if (cyc == 23) begin
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$display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr);
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if (sstr.len() != 1) $stop;
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if (sstr != "A") $stop;
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end
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else if (cyc == 30) begin
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istr <= 32'h42_00_41_00;
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end
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else if (cyc == 33) begin
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$display("istr='%s' istr%%0='%0s' sstr='%s'", istr, istr, sstr);
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if (sstr.len() != 2) $stop;
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if (sstr != "BA") $stop;
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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