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20 lines
376 B
Systemverilog
20 lines
376 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Outputs
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a, b
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);
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// verilator lint_off UNOPT
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output logic a, b;
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always_comb b = ~a;
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always_comb a = b;
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endmodule
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