mirror of
https://github.com/verilator/verilator.git
synced 2025-01-08 15:47:36 +00:00
11 lines
217 B
Coq
11 lines
217 B
Coq
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
|
//
|
||
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
|
// without warranty, 2019 by Wilson Snyder.
|
||
|
|
|
||
|
|
//bug 1381
|
||
|
|
|
||
|
|
logic root_var;
|
||
|
|
|
||
|
|
// No module statements....
|