mirror of
https://github.com/verilator/verilator.git
synced 2025-01-12 01:27:36 +00:00
33 lines
479 B
Systemverilog
33 lines
479 B
Systemverilog
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
|
//
|
||
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
|
// without warranty, 2019 by Driss Hafdi
|
||
|
|
|
||
|
|
interface Foo();
|
||
|
|
logic quux;
|
||
|
|
endinterface
|
||
|
|
|
||
|
|
module Bar();
|
||
|
|
always_comb foo.quux = '0;
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module Baz();
|
||
|
|
Foo foo();
|
||
|
|
Bar bar();
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module t (/*AUTOARG*/
|
||
|
|
// Inputs
|
||
|
|
clk
|
||
|
|
);
|
||
|
|
|
||
|
|
input clk;
|
||
|
|
|
||
|
|
Baz baz();
|
||
|
|
|
||
|
|
initial begin
|
||
|
|
$write("*-* All Finished *-*\n");
|
||
|
|
$finish;
|
||
|
|
end
|
||
|
|
endmodule
|