verilator/test_regress/t/t_forceable_var.vlt

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2021 by Geza Lore.
// SPDX-License-Identifier: CC0-1.0

`verilator_config

forceable -module "*" -var "var_*"
Implement 'forceable' attribute Using the 'forceable' directive in a configuration file, or the /* verilator forceable */ metacomment on a variable declaration will generate additional public signals that allow the specified signals to be forced/released from the C++ code. 2021-12-19 19:45:06 +00:00			`// DESCRIPTION: Verilator: Verilog Test module`
			`//`
			`// This file ONLY is placed under the Creative Commons Public Domain, for`
			`// any use, without warranty, 2021 by Geza Lore.`
			`// SPDX-License-Identifier: CC0-1.0`

			`verilator_config

			`forceable -module "" -var "var_"`