verilator/test_regress/t/t_lint_didnotconverge_bad.v

// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2012 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0

module t (/*AUTOARG*/
   // Outputs
   a, b
   );

   // verilator lint_off UNOPTFLAT

   output logic a, b;

   always_comb b = ~a;
   always_comb a = b;

endmodule
Commentary 2021-09-18 00:03:45 +00:00			`// DESCRIPTION: Verilator: Verilog Test module`
			`//`
			`// This file ONLY is placed under the Creative Commons Public Domain, for`
			`// any use, without warranty, 2012 by Wilson Snyder.`
			`// SPDX-License-Identifier: CC0-1.0`

			`module t (/AUTOARG/`
			`// Outputs`
			`a, b`
			`);`

IEEE compliant scheduler (#3384) This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278 2022-05-15 15:03:32 +00:00			`// verilator lint_off UNOPTFLAT`
Commentary 2021-09-18 00:03:45 +00:00
			`output logic a, b;`

			`always_comb b = ~a;`
			`always_comb a = b;`

			`endmodule`