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19 lines
404 B
Systemverilog
19 lines
404 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Geza Lore.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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logic [30:0] packed_data;
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logic [7:0] stream[4];
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initial begin
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packed_data = 31'h12345678;
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{>>{stream}} = packed_data;
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packed_data = {>>{stream}};
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end
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endmodule
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