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28 lines
560 B
Systemverilog
28 lines
560 B
Systemverilog
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under The Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t;
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task t;
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// verilator no_inline_task
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string trace;
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$display("== Trace Func");
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trace = $stacktrace();
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if (trace == "") $stop;
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$display("%s", trace);
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$display("== Trace Task");
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$stacktrace;
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$write("*-* All Finished *-*\n");
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$finish;
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endtask
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initial t();
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endmodule
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