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16 lines
416 B
Coq
16 lines
416 B
Coq
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2012 by Wilson Snyder.
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module t (/*AUTOARG*/);
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wire ok = 1'b0;
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// verilator lint_off PINNOCONNECT
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sub sub (.ok(ok), .nc());
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// verilator lint_on PINNOCONNECT
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endmodule
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module sub (input ok, input nc);
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initial if (ok&&nc) begin end // No unused warning
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endmodule
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