mirror of
https://github.com/verilator/verilator.git
synced 2025-01-09 16:17:36 +00:00
28 lines
512 B
Coq
28 lines
512 B
Coq
|
// $Id$
|
||
|
|
// DESCRIPTION: Verilator: Verilog Test module
|
||
|
|
//
|
||
|
|
// This file ONLY is placed into the Public Domain, for any use,
|
||
|
|
// without warranty, 2005 by Wilson Snyder.
|
||
|
|
|
||
|
|
module liblib_a (/*AUTOARG*/);
|
||
|
|
liblib_b b ();
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module liblib_b (/*AUTOARG*/);
|
||
|
|
initial begin
|
||
|
|
$write("*-* All Finished *-*\n");
|
||
|
|
$finish;
|
||
|
|
end
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module liblib_c (/*AUTOARG*/);
|
||
|
|
// Unused
|
||
|
|
initial $stop;
|
||
|
|
liblib_d d ();
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
module liblib_d (/*AUTOARG*/);
|
||
|
|
// Unused
|
||
|
|
initial $stop;
|
||
|
|
endmodule
|